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Message-ID: <20241022094429.GFZxdz_QNHHr_DCPp3@fat_crate.local>
Date: Tue, 22 Oct 2024 11:44:29 +0200
From: Borislav Petkov <bp@...en8.de>
To: Frank Li <Frank.Li@....com>
Cc: York Sun <york.sun@....com>, Tony Luck <tony.luck@...el.com>,
James Morse <james.morse@....com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Robert Richter <rric@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org, Borislav Petkov <bp@...e.de>,
devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
Priyanka Singh <priyanka.singh@....com>,
Sherry Sun <sherry.sun@....com>, Li Yang <leoyang.li@....com>
Subject: Re: [PATCH v3 3/6] EDAC/fsl_ddr: Fix bad bit shift operations
On Wed, Oct 16, 2024 at 04:31:11PM -0400, Frank Li wrote:
> From: Priyanka Singh <priyanka.singh@....com>
>
> Fix undefined behavior caused by left-shifting a negative value in the
> expression:
>
> cap_high ^ (1 << (bad_data_bit - 32))
>
> The variable 'bad_data_bit' ranges from 0 to 63. When 'bad_data_bit' is
> less than 32, 'bad_data_bit - 32' becomes negative, and left-shifting by a
> negative value in C is undefined behavior.
>
> Fix this by combining 'cap_high' and 'cap_low' into a 64-bit variable.
>
> Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx")
> Signed-off-by: Priyanka Singh <priyanka.singh@....com>
> Reviewed-by: Sherry Sun <sherry.sun@....com>
You can't keep Reviewed-by tags when you change a patch considerably: Documentation/process/submitting-patches.rst
> Signed-off-by: Li Yang <leoyang.li@....com>
What does that SOB tag mean?
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
> drivers/edac/fsl_ddr_edac.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
> index 7a9fb1202f1a0..846a4ba25342a 100644
> --- a/drivers/edac/fsl_ddr_edac.c
> +++ b/drivers/edac/fsl_ddr_edac.c
> @@ -328,6 +328,9 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
> * TODO: Add support for 32-bit wide buses
> */
> if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
> + u64 cap = (u64)cap_high << 32 | (u64)cap_low;
> + u32 s = syndrome;
> +
> sbe_ecc_decode(cap_high, cap_low, syndrome,
> &bad_data_bit, &bad_ecc_bit);
>
> @@ -338,11 +341,15 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
> fsl_mc_printk(mci, KERN_ERR,
> "Faulty ECC bit: %d\n", bad_ecc_bit);
>
> + if (bad_data_bit >= 0)
>= 0 implies != -1, right?
IOW?
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 846a4ba25342..fe822cb9b562 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -328,24 +328,21 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
* TODO: Add support for 32-bit wide buses
*/
if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
- u64 cap = (u64)cap_high << 32 | (u64)cap_low;
+ u64 cap = (u64)cap_high << 32 | cap_low;
u32 s = syndrome;
sbe_ecc_decode(cap_high, cap_low, syndrome,
&bad_data_bit, &bad_ecc_bit);
- if (bad_data_bit != -1)
- fsl_mc_printk(mci, KERN_ERR,
- "Faulty Data bit: %d\n", bad_data_bit);
- if (bad_ecc_bit != -1)
- fsl_mc_printk(mci, KERN_ERR,
- "Faulty ECC bit: %d\n", bad_ecc_bit);
-
- if (bad_data_bit >= 0)
+ if (bad_data_bit >= 0) {
+ fsl_mc_printk(mci, KERN_ERR, "Faulty Data bit: %d\n", bad_data_bit);
cap ^= 1ULL << bad_data_bit;
+ }
- if (bad_ecc_bit >= 0)
+ if (bad_ecc_bit >= 0) {
+ fsl_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d\n", bad_ecc_bit);
s ^= 1 << bad_ecc_bit;
+ }
fsl_mc_printk(mci, KERN_ERR,
"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
--
Regards/Gruss,
Boris.
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