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Message-ID: <CAAhV-H52kC_-ehzxmT5ye+XVNm5Lm=psSfAv6xqnQpkOHTMFdA@mail.gmail.com>
Date: Tue, 22 Oct 2024 17:45:34 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: maobibo <maobibo@...ngson.cn>
Cc: Thomas Gleixner <tglx@...utronix.de>, Tianrui Zhao <zhaotianrui@...ngson.cn>, 
	WANG Xuerui <kernel@...0n.name>, kvm@...r.kernel.org, loongarch@...ts.linux.dev, 
	linux-kernel@...r.kernel.org, virtualization@...ts.linux.dev, x86@...nel.org, 
	Song Gao <gaosong@...ngson.cn>
Subject: Re: [PATCH v8 3/3] irqchip/loongson-eiointc: Add extioi virt
 extension support

On Tue, Oct 22, 2024 at 5:17 PM maobibo <maobibo@...ngson.cn> wrote:
>
> Hi Huacai/Thomas,
>
> Sorry for the ping message :(
>
> Can this patch be applied int next RC version?
Queued for the next release.

Huacai

>
> Regards
> Bibo Mao
>
> On 2024/10/2 下午9:42, Thomas Gleixner wrote:
> > On Wed, Sep 11 2024 at 17:11, Huacai Chen wrote:
> >> Hi, Thomas,
> >>
> >> On Fri, Aug 30, 2024 at 5:32 PM Bibo Mao <maobibo@...ngson.cn> wrote:
> >>>
> >>> Interrupts can be routed to maximal four virtual CPUs with one HW
> >>> EIOINTC interrupt controller model, since interrupt routing is encoded with
> >>> CPU bitmap and EIOINTC node combined method. Here add the EIOINTC virt
> >>> extension support so that interrupts can be routed to 256 vCPUs on
> >>> hypervisor mode. CPU bitmap is replaced with normal encoding and EIOINTC
> >>> node type is removed, so there are 8 bits for cpu selection, at most 256
> >>> vCPUs are supported for interrupt routing.
> >> This patch is OK for me now, but seems it depends on the first two,
> >> and the first two will get upstream via loongarch-kvm tree. So is that
> >> possible to also apply this one to loongarch-kvm with your Acked-by?
> >
> > Go ahead.
> >
> > Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
> >
>

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