linux-kernel - Re: [net-next RFC PATCH v2 1/3] dt-bindings: net: dsa: Add Airoha AN8855 Gigabit Switch documentation

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Message-ID: <77e99052-a14e-4495-9197-06d98257c590@lunn.ch>
Date: Wed, 23 Oct 2024 19:39:01 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Florian Fainelli <f.fainelli@...il.com>,
	Vladimir Oltean <olteanv@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next RFC PATCH v2 1/3] dt-bindings: net: dsa: Add Airoha
 AN8855 Gigabit Switch documentation

> Well the first case that comes to mind is multiple switch and conflict.
> I have no idea if there are hw strap to configure this so I assume if a
> SoC have 2 switch (maybe of the same type), this permits to configure
> them (with reset pin and deasserting them once the base address is
> correctly configured)

Is this switch internal on an internal MDIO bus, or external?

Most PHYs and switches i've seen have strapping pins to set the base
address. It would be unusual if there was not strapping.

For the Marvell switches, the strapping moves all the MDIO
registers. This is why we have a reg at the top level in mv88e6xxx:

        ethernet-switch@0 {
            compatible = "marvell,mv88e6085";
            reg = <0>;

There is one family which use the values of 0 or 16, and each switch
uses 16 addresses. So you can put two on the bus.

> > > +  mdio:
> > > +    $ref: /schemas/net/mdio.yaml#
> > > +    unevaluatedProperties: false
> > > +    description:
> > > +      Define the relative address of the internal PHY for each port.
> > > +
> > > +      Each reg for the PHY is relative to the switch base PHY address.
> > 
> > Which is not the usual meaning of reg.
> > 
> > > +            mdio {
> > > +                #address-cells = <1>;
> > > +                #size-cells = <0>;
> > > +
> > > +                internal_phy0: phy@0 {
> > > +                    reg = <0>;
> > 
> > So given that airoha,base_smi_address defaults to 1, this is actually
> > address 1 on the MDIO bus?
> >
> 
> Yes correct. One problem I had was that moving this outside the swich
> cause panic as it does conflict with the switch PHY address...

I would make these addresses absolute, not relative. The example above
from the marvell switch, the device using addresses 16-31 has its PHYs
within that range, and we uses the absolute reg values.

	Andrew