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Message-ID: <u5gsyn22qm2syhkp3gdvvqasboq3jjybpkrsrxiisekqgpjbm3@gdawddb4kt7f>
Date: Wed, 23 Oct 2024 10:13:00 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: document SAR2130P and
SAR1130P
On Sat, Oct 19, 2024 at 07:26:41PM +0300, Dmitry Baryshkov wrote:
> Describe the last level cache controller on the SAR2130P and SAR1130P
> platforms. They have 2 banks and also a separate register set to control
> scratchpad slice.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> .../devicetree/bindings/cache/qcom,llcc.yaml | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Best regards,
Krzysztof
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