linux-kernel - Re: [PATCH v5 4/4] clk: eyeq: add driver

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Message-Id: <D534ZSNLN6G0.3HSREQ803OFIQ@bootlin.com>
Date: Wed, 23 Oct 2024 13:08:31 +0200
From: Théo Lebrun <theo.lebrun@...tlin.com>
To: "Stephen Boyd" <sboyd@...nel.org>, "Conor Dooley" <conor+dt@...nel.org>,
 "Krzysztof Kozlowski" <krzk+dt@...nel.org>, "Michael Turquette"
 <mturquette@...libre.com>, "Rob Herring" <robh@...nel.org>
Cc: <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>, "Vladimir Kondratiev"
 <vladimir.kondratiev@...ileye.com>, Grégory Clement
 <gregory.clement@...tlin.com>, "Thomas Petazzoni"
 <thomas.petazzoni@...tlin.com>, "Tawfik Bayouk"
 <tawfik.bayouk@...ileye.com>
Subject: Re: [PATCH v5 4/4] clk: eyeq: add driver

Hello Stephen,

On Thu Oct 17, 2024 at 8:48 PM CEST, Stephen Boyd wrote:
> Quoting Théo Lebrun (2024-10-07 06:49:19)
> > +/* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
> > +static const struct eqc_pll eqc_eyeq5_early_plls[] = {
> > +       { .index = EQ5C_PLL_CPU, .name = "pll-cpu",  .reg64 = 0x02C },
> > +       { .index = EQ5C_PLL_PER, .name = "pll-per",  .reg64 = 0x05C },
> > +};
> > +
> > +static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst = {
> > +       .early_pll_count        = ARRAY_SIZE(eqc_eyeq5_early_plls),
> > +       .early_plls             = eqc_eyeq5_early_plls,
> > +       .nb_late_clks = eqc_eyeq5_match_data.pll_count + eqc_eyeq5_match_data.div_count,
> > +};
> > +
> > +/* Required early for GIC timer. */
> > +static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
> > +       { .index = 0, .name = "pll-cpu", .reg64 = 0x02C },
> > +};
> > +
> > +static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = {
> > +       .early_pll_count        = ARRAY_SIZE(eqc_eyeq6h_central_early_plls),
> > +       .early_plls             = eqc_eyeq6h_central_early_plls,
> > +       .nb_late_clks = 0,
> > +};
> > +
> > +/* Required early for UART. */
>
> I still don't get this. UART isn't an early device. It's only the
> interrupt controller and the timer that matter. Does MIPS do something
> special for UARTs?

Our hardware has a PL011. That is AMBA stuff; they get probed before
platform devices by of_platform_bus_create(). "pll-per" on EyeQ5 must
be available at that time.

In concrete terms, if we don't register pll-per on EyeQ5 at
of_clk_init(), we stare at void because the serial fails probing.
I haven't digged into why EPROBE_DEFER doesn't do its job. Anyway we
don't want our serial to stall for some time during our boot process.

Thanks for the extensive review! New revision is in your inbox.

Thanks,
Théo

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com