linux-kernel - Re: [PATCH net] net: ti: iccsg-prueth: Fix 1 PPS sync

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <4c529e08-084c-43b3-ba70-982ba2555b5b@ti.com>
Date: Wed, 23 Oct 2024 17:08:07 +0530
From: Meghana Malladi <m-malladi@...com>
To: Vadim Fedorenko <vadim.fedorenko@...ux.dev>, <vigneshr@...com>,
        <horms@...nel.org>, <jan.kiszka@...mens.com>, <diogo.ivo@...mens.com>,
        <pabeni@...hat.com>, <kuba@...nel.org>, <edumazet@...gle.com>,
        <davem@...emloft.net>, <andrew+netdev@...n.ch>
CC: <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <srk@...com>,
        Roger Quadros
	<rogerq@...nel.org>, <danishanwar@...com>
Subject: Re: [PATCH net] net: ti: iccsg-prueth: Fix 1 PPS sync



On 23/10/24 15:52, Vadim Fedorenko wrote:


> On 23/10/2024 10:12, Meghana Malladi wrote:
>> The first PPS latch time needs to be calculated by the driver
>> (in rounded off seconds) and configured as the start time
>> offset for the cycle. After synchronizing two PTP clocks
>> running as master/slave, missing this would cause master
>> and slave to start immediately with some milliseconds
>> drift which causes the PPS signal to never synchronize with
>> the PTP master.
>> 
>> Fixes: 186734c15886 ("net: ti: icssg-prueth: add packet timestamping and ptp support")
>> Signed-off-by: Meghana Malladi <m-malladi@...com>
>> ---
>>   drivers/net/ethernet/ti/icssg/icssg_prueth.c | 12 ++++++++++--
>>   drivers/net/ethernet/ti/icssg/icssg_prueth.h | 11 +++++++++++
>>   2 files changed, 21 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.c b/drivers/net/ethernet/ti/icssg/icssg_prueth.c
>> index 0556910938fa..6b2cd7c898d0 100644
>> --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.c
>> +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.c
>> @@ -411,6 +411,8 @@ static int prueth_perout_enable(void *clockops_data,
>>   	struct prueth_emac *emac = clockops_data;
>>   	u32 reduction_factor = 0, offset = 0;
>>   	struct timespec64 ts;
>> +	u64 current_cycle;
>> +	u64 start_offset;
>>   	u64 ns_period;
>>   
>>   	if (!on)
>> @@ -449,8 +451,14 @@ static int prueth_perout_enable(void *clockops_data,
>>   	writel(reduction_factor, emac->prueth->shram.va +
>>   		TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET);
>>   
>> -	writel(0, emac->prueth->shram.va +
>> -		TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET);
>> +	current_cycle = icssg_readq(emac->prueth->shram.va +
>> +				    TIMESYNC_FW_WC_CYCLECOUNT_OFFSET);
>> +
>> +	/* Rounding of current_cycle count to next second */
>> +	start_offset = ((current_cycle / MSEC_PER_SEC) + 1) * MSEC_PER_SEC;
> 
> This looks more like roundup(current_cycle, MSEC_PER_SEC), let's use it
> instead of open coding.
> 

Ok sure, I will update it.

>> +
>> +	icssg_writeq(start_offset, emac->prueth->shram.va +
>> +		     TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET);
>>   
>>   	return 0;
>>   }
>> diff --git a/drivers/net/ethernet/ti/icssg/icssg_prueth.h b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
>> index 8722bb4a268a..a4af2dbcca31 100644
>> --- a/drivers/net/ethernet/ti/icssg/icssg_prueth.h
>> +++ b/drivers/net/ethernet/ti/icssg/icssg_prueth.h
>> @@ -330,6 +330,17 @@ static inline int prueth_emac_slice(struct prueth_emac *emac)
>>   extern const struct ethtool_ops icssg_ethtool_ops;
>>   extern const struct dev_pm_ops prueth_dev_pm_ops;
>>   
>> +static inline u64 icssg_readq(const void __iomem *addr)
>> +{
>> +	return readl(addr) + ((u64)readl(addr + 4) << 32);
>> +}
>> +
>> +static inline void icssg_writeq(u64 val, void __iomem *addr)
>> +{
>> +	writel(lower_32_bits(val), addr);
>> +	writel(upper_32_bits(val), addr + 4);
>> +}
>> +
>>   /* Classifier helpers */
>>   void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
>>   void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
>> 
>> base-commit: 73840ca5ef361f143b89edd5368a1aa8c2979241
>