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Message-ID: <86plnp31p5.wl-maz@kernel.org>
Date: Thu, 24 Oct 2024 17:28:22 +0100
From: Marc Zyngier <maz@...nel.org>
To: Johan Hovold <johan@...nel.org>
Cc: Sibi Sankar <quic_sibis@...cinc.com>,
	andersson@...nel.org,
	konradybcio@...nel.org,
	krzk+dt@...nel.org,
	robh+dt@...nel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	conor+dt@...nel.org,
	abel.vesa@...aro.org,
	srinivas.kandagatla@...aro.org
Subject: Re: [PATCH 0/2] X1E001DE Snapdragon Devkit for Windows

On Thu, 24 Oct 2024 17:15:28 +0100,
Johan Hovold <johan@...nel.org> wrote:
> 
> On Thu, Oct 24, 2024 at 05:02:29PM +0100, Marc Zyngier wrote:
> 
> > The only change I made was to enable the ITS for pcie5, which was
> > routed via the PCIe MSI widget instead. But that's a SoC dtsi issue
> > for which I'll post a patch separately.
> 
> That's done on purpose since the boot firmware is not setting things up
> so that we can use the ITS with PCIe5 (or PCIe3) when running in EL1
> currently.

Really? I guess they don't install a mapping for the ITS translation
register in the SMMUv3? That's rather sad.

I guess I will keep this as part of my "EL2-special" patch set then.
Feel free to ignore the patch I have just sent.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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