linux-kernel - Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node

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Message-ID: <xfy335jzh5t5a7fdrjfswerjdze3vaybf7rvkxnae3cv3xaii7@rn7iqwga2p62>
Date: Thu, 24 Oct 2024 23:42:26 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Yuanjie Yang <quic_yuanjiey@...cinc.com>
Cc: ulf.hansson@...aro.org, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, bhupesh.sharma@...aro.org, andersson@...nel.org, 
	konradybcio@...nel.org, linux-mmc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org, quic_tingweiz@...cinc.com
Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: qcs615: add SD and emmc node

On Wed, Oct 23, 2024 at 05:27:07PM +0800, Yuanjie Yang wrote:
> Add SD and emmc support to the QCS615 Ride platform. The SD controller
> and emmc controller of QCS615 are derived from SM6115. Include the
> relevant binding documents accordingly. Additionally, configure
> emmc-related and SD-related opp, power, and interconnect settings
> in the device tree.
> 
> Signed-off-by: Yuanjie Yang <quic_yuanjiey@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++
>  1 file changed, 198 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index fcba83fca7cf..3840edf13fe8 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -399,6 +399,65 @@ qfprom: efuse@...000 {
>  			#size-cells = <1>;
>  		};
>  
> +		sdhc_1: mmc@...000 {
> +			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
> +			reg = <0 0x7c4000 0 0x1000>,
> +			      <0 0x7c5000 0 0x1000>;

 <0x0 0x007c4000 0x0 0x1000> (this applies to all address nodes, so
 sdhc_2 too.


> +			reg-names = "hc",
> +				    "cqhci";
> +
> +			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hc_irq",
> +					  "pwr_irq";
> +
> +			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> +				 <&gcc GCC_SDCC1_APPS_CLK>,
> +				 <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> +			clock-names = "iface",
> +				      "core",
> +				      "xo",
> +				      "ice";
> +
> +			resets = <&gcc GCC_SDCC1_BCR>;
> +
> +			power-domains = <&rpmhpd RPMHPD_CX>;
> +			operating-points-v2 = <&sdhc1_opp_table>;
> +			iommus = <&apps_smmu 0x02c0 0x0>;
> +			interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> +					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "sdhc-ddr",
> +					     "cpu-sdhc";
> +
> +			bus-width = <8>;
> +			qcom,dll-config = <0x000f642c>;
> +			qcom,ddr-config = <0x80040868>;
> +			supports-cqe;
> +			dma-coherent;
> +			mmc-ddr-1_8v;
> +			mmc-hs200-1_8v;
> +			mmc-hs400-1_8v;
> +			mmc-hs400-enhanced-strobe;

Are these board properties or SoC properties?

> +			status = "disabled";
> +

-- 
With best wishes
Dmitry