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Message-ID: <ZxvGI0qob6YQT+YO@BLRRASHENOY1.amd.com>
Date: Fri, 25 Oct 2024 21:54:03 +0530
From: "Gautham R. Shenoy" <gautham.shenoy@....com>
To: Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>
Cc: mario.limonciello@....com, perry.yuan@....com, rafael@...nel.org,
	viresh.kumar@...aro.org, linux-pm@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/4] cpufreq/amd-pstate: Do not attempt to clear
 MSR_AMD_CPPC_ENABLE

On Wed, Oct 23, 2024 at 10:21:08AM +0000, Dhananjay Ugwekar wrote:
> MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
> it is futile, it will not take effect. Hence, return if disable (0)
> argument is passed to the msr_cppc_enable()
> 
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>


> ---
>  drivers/cpufreq/amd-pstate.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 0b4a4d69c14d..576251e61ce0 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable)
>  	int ret, cpu;
>  	unsigned long logical_proc_id_mask = 0;
>  
> +       /*
> +        * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
> +        */
> +	if (!enable)
> +		return 0;
> +
>  	if (enable == cppc_enabled)
>  		return 0;
>  
> -- 
> 2.34.1
> 

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