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Message-Id: <20241025024602.24318-3-qiuxu.zhuo@intel.com> Date: Fri, 25 Oct 2024 10:45:54 +0800 From: Qiuxu Zhuo <qiuxu.zhuo@...el.com> To: bp@...en8.de, tony.luck@...el.com Cc: tglx@...utronix.de, dave.hansen@...ux.intel.com, mingo@...hat.com, hpa@...or.com, x86@...nel.org, linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org, qiuxu.zhuo@...el.com Subject: [PATCH v3 02/10] x86/mce/intel: Use MCG_BANKCNT_MASK instead of 0xff Use the predefined MCG_BANKCNT_MASK macro instead of the hardcoded 0xff to mask the bank number bits. No functional changes intended. Reviewed-by: Tony Luck <tony.luck@...el.com> Reviewed-by: Nikolay Borisov <nik.borisov@...e.com> Reviewed-by: Sohil Mehta <sohil.mehta@...el.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@...el.com> --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf69a..b3cd2c61b11d 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static int cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); } -- 2.17.1
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