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Message-ID: <20241025074244.GB14555@noisy.programming.kicks-ass.net>
Date: Fri, 25 Oct 2024 09:42:44 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: "Christoph Lameter (Ampere)" <cl@...two.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>,
Will Deacon <will@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
Catalin Marinas <catalin.marinas@....com>,
Ingo Molnar <mingo@...hat.com>, Waiman Long <longman@...hat.com>,
Boqun Feng <boqun.feng@...il.com>, linux-mm@...ck.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-arch@...r.kernel.org
Subject: Re: [PATCH v3] Avoid memory barrier in read_seqcount() through load
acquire
On Wed, Oct 23, 2024 at 04:42:36PM -0700, Christoph Lameter (Ampere) wrote:
> On Wed, 23 Oct 2024, Peter Zijlstra wrote:
>
> > > I doubt anybody will notice, and smp_load_acquire() is the future. Any
> > > architecture that does badly on it just doesn't matter (and, as
> > > mentioned, I don't think they even exist - "smp_rmb()" is generally at
> > > least as expensive).
> >
> > Do we want to do the complementing patch and make write_seqcount_end()
> > use smp_store_release() ?
> >
> > I think at least ARM (the 32bit thing) has wmb but uses mb for
> > store_release. But I also think I don't really care about that.
>
> The proper instruction would be something like
>
> atomic_inc_release(&seqcount)
It would not be, making the increment itself atomic would make the whole
thing far more expensive.
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