[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <09ef69ee-e437-43bc-a262-3e009003d916@quicinc.com>
Date: Fri, 25 Oct 2024 14:19:44 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>
CC: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>, <quic_imrashai@...cinc.com>,
<quic_jkona@...cinc.com>,
Bartosz Golaszewski
<bartosz.golaszewski@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 8/8] arm64: dts: qcom: Add support for multimedia clock
controllers
On 10/23/2024 4:03 AM, Bjorn Andersson wrote:
> On Fri, Oct 11, 2024 at 12:28:38AM GMT, Taniya Das wrote:
>> Add support for video, camera, display0 and display1 clock
>> controllers on SA8775P platform.
>>
>
> Patch subject doesn't match expectations and for some reason commit
> message is wrapped at 60 characters. Please fix.
>
> Also please mention why dispcc1 is disabled (I'm not questioning the
> fact that it is, I just want you to document your decision)
>
Will fix in the next series of the patch.
> Regards,
> Bjorn
>
>> Reviewed-by: Jagadeesh Kona <quic_jkona@...cinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 57 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index e8dbc8d820a64f45c62edebca7ce4583a5c716e0..e56a725128e5ec228133a1b008ac2114a4682bef 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -3254,6 +3254,47 @@ llcc: system-cache-controller@...0000 {
>> interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + videocc: clock-controller@...0000 {
>> + compatible = "qcom,sa8775p-videocc";
>> + reg = <0x0 0x0abf0000 0x0 0x10000>;
>> + clocks = <&gcc GCC_VIDEO_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&sleep_clk>;
>> + power-domains = <&rpmhpd SA8775P_MMCX>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + camcc: clock-controller@...0000 {
>> + compatible = "qcom,sa8775p-camcc";
>> + reg = <0x0 0x0ade0000 0x0 0x20000>;
>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&sleep_clk>;
>> + power-domains = <&rpmhpd SA8775P_MMCX>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + dispcc0: clock-controller@...0000 {
>> + compatible = "qcom,sa8775p-dispcc0";
>> + reg = <0x0 0x0af00000 0x0 0x20000>;
>> + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&sleep_clk>,
>> + <0>, <0>, <0>, <0>,
>> + <0>, <0>, <0>, <0>;
>> + power-domains = <&rpmhpd SA8775P_MMCX>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> pdc: interrupt-controller@...0000 {
>> compatible = "qcom,sa8775p-pdc", "qcom,pdc";
>> reg = <0x0 0x0b220000 0x0 0x30000>,
>> @@ -3876,6 +3917,22 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>> };
>> };
>>
>> + dispcc1: clock-controller@...00000 {
>> + compatible = "qcom,sa8775p-dispcc1";
>> + reg = <0x0 0x22100000 0x0 0x20000>;
>> + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&sleep_clk>,
>> + <0>, <0>, <0>, <0>,
>> + <0>, <0>, <0>, <0>;
>> + power-domains = <&rpmhpd SA8775P_MMCX>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + status = "disabled";
>> + };
>> +
>> ethernet1: ethernet@...00000 {
>> compatible = "qcom,sa8775p-ethqos";
>> reg = <0x0 0x23000000 0x0 0x10000>,
>>
>> --
>> 2.45.2
>>
--
Thanks & Regards,
Taniya Das.
Powered by blists - more mailing lists