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Message-ID: <20241025111348.3810-1-Dhananjay.Ugwekar@amd.com>
Date: Fri, 25 Oct 2024 11:13:38 +0000
From: Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>
To: <peterz@...radead.org>, <mingo@...hat.com>, <rui.zhang@...el.com>,
<acme@...nel.org>, <namhyung@...nel.org>, <mark.rutland@....com>,
<alexander.shishkin@...ux.intel.com>, <jolsa@...nel.org>,
<irogers@...gle.com>, <adrian.hunter@...el.com>, <kan.liang@...ux.intel.com>,
<tglx@...utronix.de>, <bp@...en8.de>, <dave.hansen@...ux.intel.com>
CC: <ananth.narayan@....com>, <gautham.shenoy@....com>,
<kprateek.nayak@....com>, <ravi.bangoria@....com>, <x86@...nel.org>,
<linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
"Dhananjay Ugwekar" <Dhananjay.Ugwekar@....com>
Subject: [PATCH v6 00/10] Add RAPL core energy counter support for AMD CPUs
Currently the energy-cores event in the power PMU aggregates energy
consumption data at a package level. On the other hand the core energy
RAPL counter in AMD CPUs has a core scope (which means the energy
consumption is recorded separately for each core). Earlier efforts to add
the core event in the power PMU had failed [1], due to the difference in
the scope of these two events. Hence, there is a need for a new core scope
PMU.
This patchset adds a new "power_core" PMU alongside the existing
"power" PMU, which will be responsible for collecting the new
"energy-core" event.
Tested the package level and core level PMU counters with workloads
pinned to different CPUs.
Results with workload pinned to CPU 4 in core 4 on an AMD Zen4 Genoa
machine:
$ sudo perf stat --per-core -e power_core/energy-core/ -- taskset -c 4 stress-ng --matrix 1 --timeout 5s
stress-ng: info: [21250] setting to a 5 second run per stressor
stress-ng: info: [21250] dispatching hogs: 1 matrix
stress-ng: info: [21250] successful run completed in 5.00s
Performance counter stats for 'system wide':
S0-D0-C0 1 0.00 Joules power_core/energy-core/
S0-D0-C1 1 0.00 Joules power_core/energy-core/
S0-D0-C2 1 0.00 Joules power_core/energy-core/
S0-D0-C3 1 0.00 Joules power_core/energy-core/
S0-D0-C4 1 8.43 Joules power_core/energy-core/
S0-D0-C5 1 0.00 Joules power_core/energy-core/
S0-D0-C6 1 0.00 Joules power_core/energy-core/
S0-D0-C7 1 0.00 Joules power_core/energy-core/
S0-D1-C8 1 0.00 Joules power_core/energy-core/
S0-D1-C9 1 0.00 Joules power_core/energy-core/
S0-D1-C10 1 0.00 Joules power_core/energy-core/
v5 Link: https://lore.kernel.org/all/20240913152149.6317-1-Dhananjay.Ugwekar@amd.com/
v6 Changes:
* Rebase on top of V2 of Kan Liang's "PMU scope" patchset [2]
* Modify the PMU name from "power_per_core" to "power_core" and event name
from "event_per_core" to "event_core"
Base: tip/master + [2]
[1]: https://lore.kernel.org/lkml/3e766f0e-37d4-0f82-3868-31b14228868d@linux.intel.com/
[2]: https://lore.kernel.org/all/20241010142604.770192-1-kan.liang@linux.intel.com/
Dhananjay Ugwekar (9):
perf/x86/rapl: Remove the unused get_rapl_pmu_cpumask() function
perf/x86/rapl: Remove the cpu_to_rapl_pmu() function
perf/x86/rapl: Rename rapl_pmu variables
perf/x86/rapl: Make rapl_model struct global
perf/x86/rapl: Add arguments to the init and cleanup functions
perf/x86/rapl: Modify the generic variable names to *_pkg*
perf/x86/rapl: Remove the global variable rapl_msrs
perf/x86/rapl: Move the cntr_mask to rapl_pmus struct
perf/x86/rapl: Add core energy counter support for AMD CPUs
K Prateek Nayak (1):
x86/topology: Introduce topology_logical_core_id()
Documentation/arch/x86/topology.rst | 4 +
arch/x86/events/rapl.c | 412 ++++++++++++++++----------
arch/x86/include/asm/processor.h | 1 +
arch/x86/include/asm/topology.h | 1 +
arch/x86/kernel/cpu/debugfs.c | 1 +
arch/x86/kernel/cpu/topology_common.c | 1 +
6 files changed, 268 insertions(+), 152 deletions(-)
--
2.34.1
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