linux-kernel - Re: [PATCH 1/3] arm64: dts: qcom: sar2130p: add support for SAR2130P

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Message-ID: <hdygoayqsndkqdwereuvt5gfpgmhxrh2anaj7zsdm7ktuf6fus@vfhl7ubbbgsg>
Date: Sun, 27 Oct 2024 19:43:23 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Krishna Kurapati <quic_kriskura@...cinc.com>
Cc: Konrad Dybcio <konradybcio@...nel.org>, 
	Bjorn Andersson <andersson@...nel.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
	Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sar2130p: add support for SAR2130P

On Sun, Oct 27, 2024 at 12:26:33PM +0530, Krishna Kurapati wrote:
> 
> 
> On 10/27/2024 6:54 AM, Dmitry Baryshkov wrote:
> > Add DT file for the Qualcomm SAR2130P platform.
> > 
> > Co-developed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> > ---
> >   arch/arm64/boot/dts/qcom/sar2130p.dtsi | 3091 ++++++++++++++++++++++++++++++++
> >   1 file changed, 3091 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..a8edbb9e6591265644476623aec36be9147ed7a0
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
> 
> [...]
> 
> > +
> > +		usb_1: usb@...8800 {
> > +			compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
> > +			reg = <0x0 0x0a6f8800 0x0 0x400>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> > +				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> > +				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> > +				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> > +				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> > +				 <&tcsr TCSR_USB3_CLKREF_EN>;
> > +			clock-names = "cfg_noc",
> > +				      "core",
> > +				      "iface",
> > +				      "sleep",
> > +				      "mock_utmi",
> > +				      "xo";
> > +
> > +			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> > +					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> > +			assigned-clock-rates = <19200000>, <200000000>;
> > +
> > +			interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
> > +					      //<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> > +					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> > +					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> > +					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "pwr_event",
> > +					  //"hs_phy_irq",
> > +					  "dp_hs_phy_irq",
> > +					  "dm_hs_phy_irq",
> > +					  "ss_phy_irq";
> > +
> 
> I checked the hw specifics and hs_phy_irq is 349.

Thanks a lot!

> > +			power-domains = <&gcc USB30_PRIM_GDSC>;
> > +			required-opps = <&rpmhpd_opp_nom>;
> > +
> > +			resets = <&gcc GCC_USB30_PRIM_BCR>;
> > +
> > +			interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
> > +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> > +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> > +					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
> > +			interconnect-names = "usb-ddr", "apps-usb";
> > +
> > +			status = "disabled";
> > +
> > +			usb_1_dwc3: usb@...0000 {
> > +				compatible = "snps,dwc3";
> > +				reg = <0x0 0x0a600000 0x0 0xcd00>;
> > +				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
> > +				iommus = <&apps_smmu 0x20 0x0>;
> > +				phys = <&usb_1_hsphy>,
> > +				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
> > +				phy-names = "usb2-phy", "usb3-phy";
> > +
> > +				snps,has-lpm-erratum;
> > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > +				snps,is-utmi-l1-suspend;
> > +				snps,dis-u1-entry-quirk;
> > +				snps,dis-u2-entry-quirk;
> > +				snps,dis_u2_susphy_quirk;
> > +				snps,dis_u3_susphy_quirk;
> > +				snps,parkmode-disable-ss-quirk;
> > +
> > +				tx-fifo-resize;
> > +				dma-coherent;
> > +				usb-role-switch;
> > +
> 
> Ideally, neither the QAR2130P or customer designs support ID detection
> today. Not that it can't but no one is doing it. Everyone uses it in
> peripheral mode. Also on QAR2130 (which I assume is same as QXR platform on
> downstream, the role switch is provided by BQ256xx battery charger driver
> (apologies if I used the name of the driver wrong), via extcon. Since
> (AFAIK) this support is not there on upstream today and no one uses host
> mode, you can choose to drop role switch here.

I see your point (indeed, I don't have OTG configured / enabled).
However I'd still prefer to keep the usb-role-switch in the USB node and
the orientation-switch enabled for the USB+DP PHY, as those the SoC
still has those features.

-- 
With best wishes
Dmitry