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Message-ID: <b0fdfffd6b840eeabd2c9ab748915dd8@epochal.quest>
Date: Mon, 28 Oct 2024 13:42:59 -0300
From: Cody Eksal <masterr3c0rd@...chal.quest>
To: Andre Przywara <andre.przywara@....com>
Cc: linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-usb@...r.kernel.org, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen-Yu
Tsai <wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>, Samuel
Holland <samuel@...lland.org>, Parthiban <parthiban@...umiz.com>, Yangtao Li
<frank@...winnertech.com>, Florian Fainelli <florian.fainelli@...adcom.com>,
Vinod Koul <vkoul@...nel.org>, Linus Walleij <linus.walleij@...aro.org>,
Thierry Reding <treding@...dia.com>, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>, Maxime Ripard <mripard@...nel.org>, Greg
Kroah-Hartman <gregkh@...uxfoundation.org>, Yangtao Li
<tiny.windzz@...il.com>, Viresh Kumar <vireshk@...nel.org>, Nishanth Menon
<nm@...com>, Stephen Boyd <sboyd@...nel.org>, Kishon Vijay Abraham I
<kishon@...nel.org>, "Rafael J. Wysocki" <rafael@...nel.org>, Shuosheng
Huang <huangshuosheng@...winnertech.com>
Subject: Re: [PATCH 13/13] arm64: dts: allwinner: a100: Add CPU Operating
Performance Points table
On 2024/10/25 9:27 am, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:31 -0300
> Cody Eksal <masterr3c0rd@...chal.quest> wrote:
>
>> From: Shuosheng Huang <huangshuosheng@...winnertech.com>
>>
>> Add an Operating Performance Points table for the CPU cores to
>> enable Dynamic Voltage & Frequency Scaling on the A100.
>>
>> Signed-off-by: Shuosheng Huang <huangshuosheng@...winnertech.com>
>> [masterr3c0rd@...chal.quest: fix typos in -cpu-opp, use compatible]
>> Signed-off-by: Cody Eksal <masterr3c0rd@...chal.quest>
>> ---
>> .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 ++
>> .../dts/allwinner/sun50i-a100-cpu-opp.dtsi | 90
>> +++++++++++++++++++
>> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++
>> 3 files changed, 103 insertions(+)
>> create mode 100644
>> arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>>
>> diff --git
>> a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> index 29e9d24da8b6..99b1b2f7b92a 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
>> @@ -6,6 +6,7 @@
>> /dts-v1/;
>>
>> #include "sun50i-a100.dtsi"
>> +#include "sun50i-a100-cpu-opp.dtsi"
>>
>> #include <dt-bindings/gpio/gpio.h>
>>
>> @@ -67,6 +68,10 @@ &usb_otg {
>> status = "okay";
>> };
>>
>> +&cpu0 {
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> &pio {
>> vcc-pb-supply = <®_dcdc1>;
>> vcc-pc-supply = <®_eldo1>;
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> new file mode 100644
>> index 000000000000..eeb8d20f3fb4
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
>> @@ -0,0 +1,90 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (c) 2020 Yangtao Li <frank@...winnertech.com>
>> +// Copyright (c) 2020 ShuoSheng Huang
>> <huangshuosheng@...winnertech.com>
>> +
>> +/ {
>> + cpu_opp_table: cpu-opp-table {
>> + compatible = "allwinner,sun50i-a100-operating-points";
>> + nvmem-cells = <&cpu_speed_grade>;
>> + opp-shared;
>> +
>> + opp@...000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <408000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>
> Is there actually an advantage when using the three cells version?
> I wonder if we should go with just the target voltage (the first cell
> here), as done for the H616.
It probably makes sense to follow precedent; I've updated V2 to make
these single-cell.
> Apart from that it looks fine to me.
I did get a comment from Rob's bot that picked up some issues with the
namings of these nodes; I've updated that as well.
Thanks!
- Cody
> Cheers,
> Andre.
>
>> + };
>> +
>> + opp@...000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <600000000>;
>> +
>> + opp-microvolt-speed0 = <900000 900000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@...000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <816000000>;
>> +
>> + opp-microvolt-speed0 = <940000 940000 1200000>;
>> + opp-microvolt-speed1 = <900000 900000 1200000>;
>> + opp-microvolt-speed2 = <900000 900000 1200000>;
>> + };
>> +
>> + opp@...0000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1080000000>;
>> +
>> + opp-microvolt-speed0 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed1 = <980000 980000 1200000>;
>> + opp-microvolt-speed2 = <950000 950000 1200000>;
>> + };
>> +
>> + opp@...0000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1200000000>;
>> +
>> + opp-microvolt-speed0 = <1100000 1100000 1200000>;
>> + opp-microvolt-speed1 = <1020000 1020000 1200000>;
>> + opp-microvolt-speed2 = <1000000 1000000 1200000>;
>> + };
>> +
>> + opp@...0000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1320000000>;
>> +
>> + opp-microvolt-speed0 = <1160000 1160000 1200000>;
>> + opp-microvolt-speed1 = <1060000 1060000 1200000>;
>> + opp-microvolt-speed2 = <1030000 1030000 1200000>;
>> + };
>> +
>> + opp@...4000000 {
>> + clock-latency-ns = <244144>; /* 8 32k periods */
>> + opp-hz = /bits/ 64 <1464000000>;
>> +
>> + opp-microvolt-speed0 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed1 = <1180000 1180000 1200000>;
>> + opp-microvolt-speed2 = <1130000 1130000 1200000>;
>> + };
>> + };
>> +};
>> +
>> +&cpu0 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu1 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu2 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> +
>> +&cpu3 {
>> + operating-points-v2 = <&cpu_opp_table>;
>> +};
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index 6dca766ea222..747a0292ef98 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -23,6 +23,7 @@ cpu0: cpu@0 {
>> device_type = "cpu";
>> reg = <0x0>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu1: cpu@1 {
>> @@ -30,6 +31,7 @@ cpu1: cpu@1 {
>> device_type = "cpu";
>> reg = <0x1>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu2: cpu@2 {
>> @@ -37,6 +39,7 @@ cpu2: cpu@2 {
>> device_type = "cpu";
>> reg = <0x2>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>>
>> cpu3: cpu@3 {
>> @@ -44,6 +47,7 @@ cpu3: cpu@3 {
>> device_type = "cpu";
>> reg = <0x3>;
>> enable-method = "psci";
>> + clocks = <&ccu CLK_CPUX>;
>> };
>> };
>>
>> @@ -142,6 +146,10 @@ efuse@...6000 {
>> ths_calibration: calib@14 {
>> reg = <0x14 8>;
>> };
>> +
>> + cpu_speed_grade: cpu-speed-grade@1c {
>> + reg = <0x1c 0x2>;
>> + };
>> };
>>
>> watchdog@...90a0 {
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