linux-kernel - Re: [PATCH] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control

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Message-Id: <173013643645.2908148.3061264044552373982.b4-ty@kernel.org>
Date: Mon, 28 Oct 2024 18:52:21 +0000
From: Will Deacon <will@...nel.org>
To: Marc Zyngier <maz@...nel.org>,
	Russell King <linux@...linux.org.uk>,
	Catalin Marinas <catalin.marinas@....com>,
	Mark Rutland <mark.rutland@....com>,
	"Rob Herring (Arm)" <robh@...nel.org>
Cc: kernel-team@...roid.com,
	Will Deacon <will@...nel.org>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control

On Wed, 02 Oct 2024 13:43:24 -0500, Rob Herring (Arm) wrote:
> Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter
> access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual
> counters are enabled/disabled in the PMUACR_EL1 register. When UEN is
> set, the CR/ER bits control EL0 write access and must be set to disable
> write access.
> 
> With the access controls, the clearing of unused counters can be
> skipped.
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
      https://git.kernel.org/will/c/0bbff9ed8165

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev