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Message-Id: <20241028-upstream_s32cc_gmac-v4-1-03618f10e3e2@oss.nxp.com>
Date: Mon, 28 Oct 2024 21:24:43 +0100
From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@...nel.org>
To: Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>, "David S. Miller" <davem@...emloft.net>,
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Russell King <linux@...linux.org.uk>, Shawn Guo <shawnguo@...nel.org>,
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Pengutronix Kernel Team <kernel@...gutronix.de>,
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Cc: linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org, linux-arm-msm@...r.kernel.org, imx@...ts.linux.dev,
devicetree@...r.kernel.org, NXP S32 Linux Team <s32@....com>,
"Jan Petrous (OSS)" <jan.petrous@....nxp.com>,
Jacob Keller <jacob.e.keller@...el.com>
Subject: [PATCH v4 01/16] net: driver: stmmac: Fix CSR divider comment
From: "Jan Petrous (OSS)" <jan.petrous@....nxp.com>
The comment in declaration of STMMAC_CSR_250_300M
incorrectly describes the constant as '/* MDC = clk_scr_i/122 */'
but the DWC Ether QOS Handbook version 5.20a says it is
CSR clock/124.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@....nxp.com>
Reviewed-by: Jacob Keller <jacob.e.keller@...el.com>
---
include/linux/stmmac.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index d79ff252cfdc..75cbfb576358 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -33,7 +33,7 @@
#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
-#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
+#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */
/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR 0x0
--
2.46.0
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