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Message-ID: <CAF6AEGst2uOosTiu63mr95w=Km1bMEQbryxEAGRpiUKqr_rM-g@mail.gmail.com>
Date: Mon, 28 Oct 2024 14:13:53 -0700
From: Rob Clark <robdclark@...il.com>
To: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
Cc: will@...nel.org, robin.murphy@....com, joro@...tes.org, jgg@...pe.ca,
jsnitsel@...hat.com, robh@...nel.org, krzysztof.kozlowski@...aro.org,
quic_c_gdjako@...cinc.com, dmitry.baryshkov@...aro.org, iommu@...ts.linux.dev,
linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v16 3/5] iommu/arm-smmu: add support for PRR bit setup
On Tue, Oct 8, 2024 at 5:54 AM Bibek Kumar Patro
<quic_bibekkum@...cinc.com> wrote:
>
> Add an adreno-smmu-priv interface for drm/msm to call
> into arm-smmu-qcom and initiate the PRR bit setup or reset
> sequence as per request.
>
> This will be used by GPU to setup the PRR bit and related
> configuration registers through adreno-smmu private
> interface instead of directly poking the smmu hardware.
>
> Suggested-by: Rob Clark <robdclark@...il.com>
Reviewed-by: Rob Clark <robdclark@...il.com>
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@...cinc.com>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++++
> drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++
> include/linux/adreno-smmu-priv.h | 10 +++++-
> 3 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 6e0a2a43e45a..38ac9cab763b 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -25,6 +25,7 @@
>
> #define CPRE (1 << 1)
> #define CMTLB (1 << 0)
> +#define GFX_ACTLR_PRR (1 << 5)
>
> static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
> {
> @@ -109,6 +110,40 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina
> arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg);
> }
>
> +static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set)
> +{
> + struct arm_smmu_domain *smmu_domain = (void *)cookie;
> + struct arm_smmu_device *smmu = smmu_domain->smmu;
> + const struct device_node *np = smmu->dev->of_node;
> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
> + u32 reg = 0;
> +
> + if (of_device_is_compatible(np, "qcom,smmu-500") &&
> + of_device_is_compatible(np, "qcom,adreno-smmu")) {
> + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR);
> + reg &= ~GFX_ACTLR_PRR;
> + if (set)
> + reg |= FIELD_PREP(GFX_ACTLR_PRR, 1);
> + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg);
> + }
> +}
> +
> +static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr)
> +{
> + struct arm_smmu_domain *smmu_domain = (void *)cookie;
> + struct arm_smmu_device *smmu = smmu_domain->smmu;
> + const struct device_node *np = smmu->dev->of_node;
> +
> + if (of_device_is_compatible(np, "qcom,smmu-500") &&
> + of_device_is_compatible(np, "qcom,adreno-smmu")) {
> + writel_relaxed(lower_32_bits(page_addr),
> + smmu->base + ARM_SMMU_GFX_PRR_CFG_LADDR);
> +
> + writel_relaxed(upper_32_bits(page_addr),
> + smmu->base + ARM_SMMU_GFX_PRR_CFG_UADDR);
> + }
> +}
> +
> #define QCOM_ADRENO_SMMU_GPU_SID 0
>
> static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
> @@ -249,6 +284,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
> priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
> priv->set_stall = qcom_adreno_smmu_set_stall;
> priv->resume_translation = qcom_adreno_smmu_resume_translation;
> + priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit;
> + priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr;
>
> return 0;
> }
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> index e2aeb511ae90..2dbf3243b5ad 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type {
> #define ARM_SMMU_SCTLR_M BIT(0)
>
> #define ARM_SMMU_CB_ACTLR 0x4
> +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008
> +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C
>
> #define ARM_SMMU_CB_RESUME 0x8
> #define ARM_SMMU_RESUME_TERMINATE BIT(0)
> diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h
> index c637e0997f6d..03466eb16933 100644
> --- a/include/linux/adreno-smmu-priv.h
> +++ b/include/linux/adreno-smmu-priv.h
> @@ -49,7 +49,13 @@ struct adreno_smmu_fault_info {
> * before set_ttbr0_cfg(). If stalling on fault is enabled,
> * the GPU driver must call resume_translation()
> * @resume_translation: Resume translation after a fault
> - *
> + * @set_prr_bit: Extendible interface to be used by GPU to modify the
> + * ACTLR register bits, currently used to configure
> + * Partially-Resident-Region (PRR) bit for feature's
> + * setup and reset sequence as requested.
> + * @set_prr_addr: Configure the PRR_CFG_*ADDR register with the
> + * physical address of PRR page passed from
> + * GPU driver.
> *
> * The GPU driver (drm/msm) and adreno-smmu work together for controlling
> * the GPU's SMMU instance. This is by necessity, as the GPU is directly
> @@ -67,6 +73,8 @@ struct adreno_smmu_priv {
> void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
> void (*set_stall)(const void *cookie, bool enabled);
> void (*resume_translation)(const void *cookie, bool terminate);
> + void (*set_prr_bit)(const void *cookie, bool set);
> + void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr);
> };
>
> #endif /* __ADRENO_SMMU_PRIV_H */
> --
> 2.34.1
>
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