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Message-ID: <CACT4zj9C0NhL02zv89qB2SgBpgit_Dj4-9i+JCq_XHiOu66tGA@mail.gmail.com>
Date: Mon, 28 Oct 2024 08:21:54 +0800
From: Ben Chuang <benchuanggli@...il.com>
To: Georg Gottleuber <ggo@...edocomputers.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, adrian.hunter@...el.com, 
	victor.shih@...esyslogic.com.tw, greg.tu@...esyslogic.com.tw, 
	ben.chuang@...esyslogic.com.tw, HL.Liu@...esyslogic.com.tw, 
	Lucas.Lai@...esyslogic.com.tw, victorshihgli@...il.com, 
	linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Werner Sembach <wse@...edocomputers.com>, cs@...edo.de
Subject: Re: [PATCH 1/2] mmc: sdhci-pci-gli: GL9767: Fix low power mode on the
 set clock function

Hi Georg,

Thanks for your test.
If there is no confidential information,
Can you share some pci/acpi configuration or the s0ix self test log on
AMD/Intel laptop?

Best regards,
Ben Chuang

On Fri, Oct 25, 2024 at 11:40 PM Georg Gottleuber
<ggo@...edocomputers.com> wrote:
>
> Hello Ben, hello Uffe,
>
> thank you for this fix.
>
> Am 25.10.24 um 15:22 schrieb Ulf Hansson:
> > + Georg
> >
> > On Fri, 25 Oct 2024 at 08:01, Ben Chuang <benchuanggli@...il.com> wrote:
> >>
> >> From: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> >>
> >> On sdhci_gl9767_set_clock(), the vendor header space(VHS) is read-only
> >> after calling gl9767_disable_ssc_pll() and gl9767_set_ssc_pll_205mhz().
> >> So the low power negotiation mode cannot be enabled again.
> >> Introduce gl9767_set_low_power_negotiation() function to fix it.
> >>
> >> The explanation process is as below.
> >>
> >> static void sdhci_gl9767_set_clock()
> >> {
> >>         ...
> >>         gl9767_vhs_write();
> >>         ...
> >>         value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> >>         pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); <--- (a)
> >>
> >>         gl9767_disable_ssc_pll(); <--- (b)
> >>         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> >>
> >>         if (clock == 0)
> >>                 return;  <-- (I)
> >>
> >>         ...
> >>         if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
> >>                 ...
> >>                 gl9767_set_ssc_pll_205mhz(); <--- (c)
> >>         }
> >>         ...
> >>         value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> >>         pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); <-- (II)
> >>         gl9767_vhs_read();
> >> }
> >>
> >> (a) disable low power negotiation mode. When return on (I), the low power
> >> mode is disabled.  After (b) and (c), VHS is read-only, the low power mode
> >> cannot be enabled on (II).
> >>
> >> Fixes: d2754355512e ("mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767")
> >
> > Is this the same problem as being reported in
> > https://lore.kernel.org/all/41c1c88a-b2c9-4c05-863a-467785027f49@tuxedocomputers.com/
> >
> > ?
>
> Yes, this patch fixes
> https://bugzilla.kernel.org/show_bug.cgi?id=219284
>
> This makes my patch obsolete.
>
> Kind regards,
> Georg

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