linux-kernel - Re: [PATCH v3 2/3] arm64: dts: qcom: x1e80100: Describe TLMM pins for SDC2

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Message-ID: <Zx9P+HQMOkJsJGcj@linaro.org>
Date: Mon, 28 Oct 2024 10:48:56 +0200
From: Abel Vesa <abel.vesa@...aro.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konradybcio@...nel.org>,
	Johan Hovold <johan@...nel.org>,
	Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
	linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: x1e80100: Describe TLMM pins
 for SDC2

On 24-10-25 20:34:19, Konrad Dybcio wrote:
> On 22.10.2024 12:46 PM, Abel Vesa wrote:
> > Describe the SDC2 default and sleep state pins configuration
> > in TLMM. Do this in SoC dtsi file since they will be shared
> > across multiple boards.
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > ---
> 
> Not very useful on its own but okay..

Fair enough. For some reason, I'm not able to get sdc4 pinconf
to work. And there is no board that has a slot populated for it.
So I split the pinconf for sdc2 into a separate patch to make it more
obvious that sdc4 one is missing.

Let me know if you still want to me to squash this into the patch that
adds the controller nodes.

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> 
> Konrad

Thanks for reviewing.

Abel