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Message-ID: <20241028020251.8085-5-mario.limonciello@amd.com>
Date: Sun, 27 Oct 2024 21:02:42 -0500
From: Mario Limonciello <mario.limonciello@....com>
To: Borislav Petkov <bp@...en8.de>, Hans de Goede <hdegoede@...hat.com>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
CC: <x86@...nel.org>, "Gautham R . Shenoy" <gautham.shenoy@....com>, "Mario
Limonciello" <mario.limonciello@....com>, Perry Yuan <perry.yuan@....com>,
<linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-pm@...r.kernel.org>, <platform-driver-x86@...r.kernel.org>, "Shyam
Sundar S K" <Shyam-sundar.S-k@....com>
Subject: [PATCH v5 04/13] x86/msr-index: define AMD heterogeneous CPU related MSR
From: Perry Yuan <perry.yuan@....com>
Introduces new MSR registers for AMD hardware feedback support.
These registers enable the system to provide workload classification
and configuration capabilities.
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
Signed-off-by: Perry Yuan <perry.yuan@....com>
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
---
arch/x86/include/asm/msr-index.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3ae84c3b8e6db..0cd5ffe50f4a4 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -712,6 +712,11 @@
#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
+/* AMD Hardware Feedback Support MSRs */
+#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500
+#define AMD_WORKLOAD_CLASS_ID 0xc0000501
+#define AMD_WORKLOAD_HRST 0xc0000502
+
/* AMD Last Branch Record MSRs */
#define MSR_AMD64_LBR_SELECT 0xc000010e
--
2.43.0
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