linux-kernel - Re: [PATCH] arm64: dts: qcom: Add coresight nodes for QCS615

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Message-ID: <3f90b3d6-9637-47b7-ad8a-ff43cb28ad32@quicinc.com>
Date: Mon, 28 Oct 2024 08:54:29 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Jinlong Mao
	<quic_jinlmao@...cinc.com>,
        Tao Zhang <quic_taozha@...cinc.com>
Subject: Re: [PATCH] arm64: dts: qcom: Add coresight nodes for QCS615



On 10/26/2024 2:47 AM, Konrad Dybcio wrote:
> On 17.10.2024 5:00 AM, Jie Gan wrote:
>> Add following coresight components on QCS615, EUD, TMC/ETF, TPDM, dynamic
>> Funnel, TPDA, Replicator and ETM.
>>
>> Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
>> ---
>> Already checked by command:dtbs_check W=1.
>>
>> Dependencies:
>> 1. Depends on qcs615 base dtsi change:
>> https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/
>> 2. Depends on qcs615 AOSS_QMP change:
>> https://lore.kernel.org/linux-arm-msm/20241017025313.2028120-4-quic_chunkaid@quicinc.com/
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 1632 ++++++++++++++++++++++++++
>>   1 file changed, 1632 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 856b40e20cf3..87cca5de018e 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -202,6 +202,18 @@ l3_0: l3-cache {
>>   		};
>>   	};
>>   
>> +	dummy_eud: dummy_sink {
> 
> Node names (after the ':' and before the '{' signs) can't contain
> underscores, use '-' instead.
Sure, will fix it.

> 
> [...]
> 
>> +		stm@...2000 {
>> +			compatible = "arm,coresight-stm", "arm,primecell";
>> +			reg = <0x0 0x6002000 0x0 0x1000>,
> 
> Please pad the non-zero address part to 8 hex digits with leading
> zeroes, across the board
Will fix it.

> 
> This looks like a lot of nodes, all enabled by default. Will this run
> on a production-fused device?
Yes, usually Coresight nodes are enabled by default. Those nodes can run 
on the commercial devices.

> 
> Konrad

Thanks,
Jie