linux-kernel - Re: [PATCH v8 10/13] dt-bindings: mips: cpu: Add property for broken HCI information

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Message-ID: <87seseao3z.fsf@BLaptop.bootlin.com>
Date: Tue, 29 Oct 2024 17:08:16 +0100
From: Gregory CLEMENT <gregory.clement@...tlin.com>
To: Aleksandar Rikalo <arikalo@...il.com>, Krzysztof Kozlowski
 <krzk@...nel.org>
Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>, Rob Herring
 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Vladimir Kondratiev
 <vladimir.kondratiev@...ileye.com>, Theo Lebrun <theo.lebrun@...tlin.com>,
 Arnd Bergmann <arnd@...db.de>, devicetree@...r.kernel.org, Djordje
 Todorovic <djordje.todorovic@...cgroup.com>, Chao-ying Fu
 <cfu@...ecomp.com>, Daniel Lezcano <daniel.lezcano@...aro.org>, Geert
 Uytterhoeven <geert@...ux-m68k.org>, Greg Ungerer <gerg@...nel.org>, Hauke
 Mehrtens <hauke@...ke-m.de>, Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
 Jiaxun Yang <jiaxun.yang@...goat.com>, linux-kernel@...r.kernel.org,
 linux-mips@...r.kernel.org, Marc Zyngier <maz@...nel.org>, Paul Burton
 <paulburton@...nel.org>, Peter Zijlstra <peterz@...radead.org>, Serge
 Semin <fancer.lancer@...il.com>, Tiezhu Yang <yangtiezhu@...ngson.cn>
Subject: Re: [PATCH v8 10/13] dt-bindings: mips: cpu: Add property for
 broken HCI information

Hi,

> On Tue, Oct 29, 2024 at 8:03 AM Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
>> > diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml
>> > index a85137add668..57e93c07ab1b 100644
>> > --- a/Documentation/devicetree/bindings/mips/cpus.yaml
>> > +++ b/Documentation/devicetree/bindings/mips/cpus.yaml
>> > @@ -47,6 +47,12 @@ properties:
>> >    clocks:
>> >      maxItems: 1
>> >
>> > +  cm3-l2-config-hci-broken:
>>
>> Are these names - cm3, l2, hci - obvious and known in MIPS? HCI usually
>> means something else - see drivers/bluetooth/ and drivers/nfc/
>
> I would say yes. At least the name "CM3" (Coherence Manager 3) is
> common knowledge.
> L2 HCI (L2 Hardware Cache Initialization) is a feature of CM3 that is
> non-functional on some systems.
>
>> Is this property applicable for all MIPS vendors? There is no vendor
>> prefix here, so this is generic for this architecture, right?
>
> I'm honestly not sure if this is something that only one vendor will use.
> Theoretically, there could be more. Perhaps Gregory CLEMENT can give a
> more precise answer.

All I know is that this property is needed because of an issue in this
CPU designed by Imagination. So, to my knowledge, it is present at least
on some Imagination CPUs, but since it is an issue, I think any other
MIPS designer could encounter the same problem.

Gregory

>
> Best Regards,
> Aleksandar

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com