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Message-ID: <20241029031222.1653123-3-quic_liuxin@quicinc.com>
Date: Tue, 29 Oct 2024 11:12:21 +0800
From: Xin Liu <quic_liuxin@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <kernel@...cinc.com>,
<quic_jiegan@...cinc.com>, <quic_aiquny@...cinc.com>,
<quic_tingweiz@...cinc.com>
Subject: [PATCH v1 2/3] arm64: dts: qcom: qcs8300: Add watchdog node
Add the watchdog node for QCS8300 SoC.
Signed-off-by: Xin Liu <quic_liuxin@...cinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 2c35f96c3f28..876eb16be11c 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -1122,6 +1122,12 @@ intc: interrupt-controller@...00000 {
redistributor-stride = <0x0 0x20000>;
};
+ watchdog@...10000 {
+ compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
+ reg = <0x0 0x17c10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
memtimer: timer@...20000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
--
2.34.1
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