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Message-Id: <ac00d2b923bf66122ad24059d6eab6039137ad63.1730172244.git.Sandor.yu@nxp.com>
Date: Tue, 29 Oct 2024 14:02:13 +0800
From: Sandor Yu <Sandor.yu@....com>
To: dmitry.baryshkov@...aro.org,
andrzej.hajda@...el.com,
neil.armstrong@...aro.org,
Laurent.pinchart@...asonboard.com,
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robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
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s.hauer@...gutronix.de,
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vkoul@...nel.org,
dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
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Cc: kernel@...gutronix.de,
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sam@...nborg.org,
Rob Herring <robh@...nel.org>
Subject: [PATCH v18 5/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY
Add bindings for Freescale iMX8MQ DP and HDMI PHY.
Signed-off-by: Sandor Yu <Sandor.yu@....com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
v9->v18:
*No change.
.../bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
new file mode 100644
index 0000000000000..c17a645e71bad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-dp-hdmi-phy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8mq-dp-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
+
+maintainers:
+ - Sandor Yu <sandor.yu@....com>
+
+properties:
+ compatible:
+ const: fsl,imx8mq-hdptx-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PHY reference clock.
+ - description: APB clock.
+
+ clock-names:
+ items:
+ - const: ref
+ - const: apb
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mq-clock.h>
+ #include <dt-bindings/phy/phy.h>
+ dp_phy: phy@...00000 {
+ compatible = "fsl,imx8mq-hdptx-phy";
+ reg = <0x32c00000 0x100000>;
+ #phy-cells = <0>;
+ clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ clock-names = "ref", "apb";
+ };
--
2.34.1
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