linux-kernel - Re: [PATCH] clk: meson clk-phase: fix division by zero in meson_clk_degrees_to

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <1j34kfuszi.fsf@starbuckisacylon.baylibre.com>
Date: Tue, 29 Oct 2024 11:02:41 +0100
From: Jerome Brunet <jbrunet@...libre.com>
To: Zicheng Qu <quzicheng@...wei.com>
Cc: <neil.armstrong@...aro.org>,  <mturquette@...libre.com>,
  <sboyd@...nel.org>,  <khilman@...libre.com>,
  <martin.blumenstingl@...glemail.com>,
  <linux-amlogic@...ts.infradead.org>,  <linux-clk@...r.kernel.org>,
  <linux-arm-kernel@...ts.infradead.org>,  <linux-kernel@...r.kernel.org>,
  <tanghui20@...wei.com>,  <zhangqiao22@...wei.com>,
  <judy.chenhui@...wei.com>
Subject: Re: [PATCH] clk: meson clk-phase: fix division by zero in
 meson_clk_degrees_to_val()

On Sat 26 Oct 2024 at 07:26, Zicheng Qu <quzicheng@...wei.com> wrote:

> In the meson_clk_phase_set_phase() function, the variable phase->ph.width
> is of type u8, with a range of 0 to 255. When calling

Thanks for noticing this. Some remarks though ...

> meson_clk_degrees_to_val with width as an argument, if width > 8,
> phase_step(width) will return 0. Lead to a division by zero error in
> DIV_ROUND_CLOSEST(). The same issue exists in the
> meson_clk_triphase_set_phase() and meson_sclk_ws_inv_set_phase().

It would have been worth noting that the issue is hypothetical given
that all existing instance of the mentioned drivers have a phase width of 1.

>
> Fixes: 7b70689b07c1 ("clk: meson: add sclk-ws driver")

The "problem" did not appear with this commit.

> Cc: <stable@...r.kernel.org>
> Signed-off-by: Zicheng Qu <quzicheng@...wei.com>
> ---
>  drivers/clk/meson/clk-phase.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c
> index c1526fbfb6c4..b88d59b7a90d 100644
> --- a/drivers/clk/meson/clk-phase.c
> +++ b/drivers/clk/meson/clk-phase.c
> @@ -51,6 +51,9 @@ static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
>  	struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
>  	unsigned int val;
>  
> +	if (phase->ph.width > 8)
> +		return -EINVAL;
> +

I don't think erroring out on this condition is correct.
A phase encoded on more than 8 bit is valid.

I think casting width to 'unsigned int' in phase_step() would be better.

>  	val = meson_clk_degrees_to_val(degrees, phase->ph.width);
>  	meson_parm_write(clk->map, &phase->ph, val);
>  
> @@ -110,6 +113,9 @@ static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees)
>  	struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk);
>  	unsigned int val;
>  
> +	if (tph->ph0.width > 8)
> +		return -EINVAL;
> +
>  	val = meson_clk_degrees_to_val(degrees, tph->ph0.width);
>  	meson_parm_write(clk->map, &tph->ph0, val);
>  	meson_parm_write(clk->map, &tph->ph1, val);
> @@ -167,6 +173,9 @@ static int meson_sclk_ws_inv_set_phase(struct clk_hw *hw, int degrees)
>  	struct meson_sclk_ws_inv_data *tph = meson_sclk_ws_inv_data(clk);
>  	unsigned int val;
>  
> +	if (tph->ph.width > 8)
> +		return -EINVAL;
> +
>  	val = meson_clk_degrees_to_val(degrees, tph->ph.width);
>  	meson_parm_write(clk->map, &tph->ph, val);
>  	meson_parm_write(clk->map, &tph->ws, val ? 0 : 1);

-- 
Jerome