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Message-ID: <173029979246.3137.4752160860801797555.tip-bot2@tip-bot2>
Date: Wed, 30 Oct 2024 14:49:52 -0000
From: "tip-bot2 for Chao-ying Fu" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: "Chao-ying Fu" <cfu@...ecomp.com>,
Dragan Mladjenovic <dragan.mladjenovic@...mia.com>,
Aleksandar Rikalo <arikalo@...il.com>, Thomas Gleixner <tglx@...utronix.de>,
Serge Semin <fancer.lancer@...il.com>,
Gregory CLEMENT <gregory.clement@...tlin.com>, x86@...nel.org,
linux-kernel@...r.kernel.org, maz@...nel.org
Subject: [tip: irq/core] irqchip/mips-gic: Setup defaults in each cluster
The following commit has been merged into the irq/core branch of tip:
Commit-ID: c7c0d13d1d308b6e2a3d69274b38fca0167081df
Gitweb: https://git.kernel.org/tip/c7c0d13d1d308b6e2a3d69274b38fca0167081df
Author: Chao-ying Fu <cfu@...ecomp.com>
AuthorDate: Mon, 28 Oct 2024 18:59:25 +01:00
Committer: Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Wed, 30 Oct 2024 15:41:18 +01:00
irqchip/mips-gic: Setup defaults in each cluster
In multi-cluster MIPS I6500 systems, there is a GIC per cluster.
The default shared interrupt setup configured in gic_of_init() applies only
to the GIC in the cluster containing the boot CPU, leaving the GICs of
other clusters unconfigured.
Configure the other clusters as well.
Signed-off-by: Chao-ying Fu <cfu@...ecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@...mia.com>
Signed-off-by: Aleksandar Rikalo <arikalo@...il.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Tested-by: Serge Semin <fancer.lancer@...il.com>
Tested-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Link: https://lore.kernel.org/all/20241028175935.51250-4-arikalo@gmail.com
---
drivers/irqchip/irq-mips-gic.c | 30 ++++++++++++++++++++++++------
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 29bdfdc..d93a076 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -764,7 +764,7 @@ static int gic_cpu_startup(unsigned int cpu)
static int __init gic_of_init(struct device_node *node,
struct device_node *parent)
{
- unsigned int cpu_vec, i, gicconfig;
+ unsigned int cpu_vec, i, gicconfig, cl, nclusters;
unsigned long reserved;
phys_addr_t gic_base;
struct resource res;
@@ -845,11 +845,29 @@ static int __init gic_of_init(struct device_node *node,
board_bind_eic_interrupt = &gic_bind_eic_interrupt;
- /* Setup defaults */
- for (i = 0; i < gic_shared_intrs; i++) {
- change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
- change_gic_trig(i, GIC_TRIG_LEVEL);
- write_gic_rmask(i);
+ /*
+ * Initialise each cluster's GIC shared registers to sane default
+ * values.
+ * Otherwise, the IPI set up will be erased if we move code
+ * to gic_cpu_startup for each cpu.
+ */
+ nclusters = mips_cps_numclusters();
+ for (cl = 0; cl < nclusters; cl++) {
+ if (cl == cpu_cluster(¤t_cpu_data)) {
+ for (i = 0; i < gic_shared_intrs; i++) {
+ change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
+ change_gic_trig(i, GIC_TRIG_LEVEL);
+ write_gic_rmask(i);
+ }
+ } else {
+ mips_cm_lock_other(cl, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
+ for (i = 0; i < gic_shared_intrs; i++) {
+ change_gic_redir_pol(i, GIC_POL_ACTIVE_HIGH);
+ change_gic_redir_trig(i, GIC_TRIG_LEVEL);
+ write_gic_redir_rmask(i);
+ }
+ mips_cm_unlock_other();
+ }
}
return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
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