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Message-ID: <CAA8EJpoMHrTw069bkSiNG3q6J2SftGBCbYwgpr4yjeporVK1nw@mail.gmail.com>
Date: Wed, 30 Oct 2024 05:14:57 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Yongbang Shi <shiyongbang@...wei.com>
Cc: xinliang.liu@...aro.org, tiantao6@...ilicon.com,
maarten.lankhorst@...ux.intel.com, mripard@...nel.org, tzimmermann@...e.de,
airlied@...il.com, daniel@...ll.ch, kong.kongxinwei@...ilicon.com,
liangjian010@...wei.com, chenjianmin@...wei.com, lidongming5@...wei.com,
libaihan@...wei.com, shenjian15@...wei.com, shaojijie@...wei.com,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 drm-dp 2/4] drm/hisilicon/hibmc: add dp link moduel in hibmc
On Tue, 29 Oct 2024 at 16:15, Yongbang Shi <shiyongbang@...wei.com> wrote:
>
> > On Tue, Oct 22, 2024 at 08:41:46PM +0800, Yongbang Shi wrote:
> >> From: baihan li <libaihan@...wei.com>
> >>
> >> Add link training process functions in this moduel.
> > We should probably have a bounty for a developer who finally writes a
> > generic DP link training helpers.
> >
> >> Signed-off-by: baihan li <libaihan@...wei.com>
> > Missing SoB
> >
> >> ---
> >> ChangeLog:
> >> v1 -> v2:
> >> - using drm_dp_* functions implement dp link training process, suggested by Jani Nikula.
> >> - fix build errors reported by kernel test robot <lkp@...el.com>
> >> Closes: https://lore.kernel.org/oe-kbuild-all/202410031735.8iRZZR6T-lkp@intel.com/
> >> v1:https://lore.kernel.org/all/20240930100610.782363-1-shiyongbang@huawei.com/
> >> ---
> >> drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +-
> >> drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 344 +++++++++++++++++++
> >> drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h | 25 ++
> >> 3 files changed, 370 insertions(+), 1 deletion(-)
> >> create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
> >> create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.h
> >>
> >> diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/hisilicon/hibmc/Makefile
> >> index 8770ec6dfffd..94d77da88bbf 100644
> >> --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile
> >> +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile
> >> @@ -1,5 +1,5 @@
> >> # SPDX-License-Identifier: GPL-2.0-only
> >> hibmc-drm-y := hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm_i2c.o \
> >> - dp/dp_aux.o
> >> + dp/dp_aux.o dp/dp_link.o
> >>
> >> obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc-drm.o
> >> diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
> >> new file mode 100644
> >> index 000000000000..b02a536e0689
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
> >> @@ -0,0 +1,344 @@
> >> +// SPDX-License-Identifier: GPL-2.0-or-later
> >> +// Copyright (c) 2024 Hisilicon Limited.
> >> +
> >> +#include <linux/delay.h>
> >> +#include <drm/drm_device.h>
> >> +#include <drm/drm_print.h>
> >> +#include "dp_comm.h"
> >> +#include "dp_reg.h"
> >> +#include "dp_link.h"
> >> +#include "dp_aux.h"
> >> +
> >> +const u8 link_rate_map[] = {DP_LINK_BW_1_62, DP_LINK_BW_2_7,
> >> + DP_LINK_BW_5_4, DP_LINK_BW_8_1};
> >> +
> >> +static int dp_link_training_configure(struct dp_dev *dp)
> >> +{
> >> + u8 buf[2];
> >> + int ret;
> >> +
> >> + /* DP 2 lane */
> >> + dp_write_bits(dp->base + DP_PHYIF_CTRL0, DP_CFG_LANE_DATA_EN,
> >> + dp->link.cap.lanes == DP_LANE_NUM_2 ? 0x3 : 0x1);
> >> + dp_write_bits(dp->base + DP_DPTX_GCTL0, DP_CFG_PHY_LANE_NUM,
> >> + dp->link.cap.lanes == DP_LANE_NUM_2 ? 0x1 : 0);
> >> +
> >> + /* enhanced frame */
> >> + dp_write_bits(dp->base + DP_VIDEO_CTRL, DP_CFG_STREAM_FRAME_MODE, 0x1);
> >> +
> >> + /* set rate and lane count */
> >> + buf[0] = dp_get_link_rate(dp->link.cap.link_rate);
> >> + buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes;
> >> + ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
> >> + if (ret != sizeof(buf)) {
> >> + drm_err(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret);
> >> + return ret;
> >> + }
> >> +
> >> + /* set 8b/10b and downspread */
> >> + buf[0] = 0x10;
> >> + buf[1] = 0x1;
> >> + ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));
> >> + if (ret != sizeof(buf))
> >> + drm_err(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\n", ret);
> >> +
> >> + ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd);
> >> + if (ret)
> >> + drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret);
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static int dp_link_pattern2dpcd(struct dp_dev *dp, enum dp_pattern_e pattern)
> >> +{
> >> + switch (pattern) {
> >> + case DP_PATTERN_NO:
> >> + return DP_TRAINING_PATTERN_DISABLE;
> >> + case DP_PATTERN_TPS1:
> >> + return DP_TRAINING_PATTERN_1;
> >> + case DP_PATTERN_TPS2:
> >> + return DP_TRAINING_PATTERN_2;
> >> + case DP_PATTERN_TPS3:
> >> + return DP_TRAINING_PATTERN_3;
> >> + case DP_PATTERN_TPS4:
> >> + return DP_TRAINING_PATTERN_4;
> >> + default:
> >> + drm_err(dp->dev, "dp link unknown pattern %d\n", pattern);
> >> + return -EINVAL;
> > Why do you need the extra defines / wrappers? Can you use
> > DP_TRAINING_PATTERN_foo directly?
>
> Hi Dmitry,
> Thanks for your all of these good advices and questions. I will resply as soon as possible.
> For this point, I also need this enum dp_pattern_e value to write in my dp reg at TPS stage, so I made this map here.
I'd suggest to do it other way around: use standard defines and when
necessary map them for the register write.
--
With best wishes
Dmitry
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