linux-kernel - Re: [PATCH v4 0/4] Relax canonical checks on some arch msrs

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Message-ID: <ZyKjo-XpaNjIkMdA@google.com>
Date: Wed, 30 Oct 2024 14:22:43 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Maxim Levitsky <mlevitsk@...hat.com>
Cc: kvm@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>, 
	Paolo Bonzini <pbonzini@...hat.com>, Ingo Molnar <mingo@...hat.com>, 
	Vitaly Kuznetsov <vkuznets@...hat.com>, linux-kernel@...r.kernel.org, 
	"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org, Borislav Petkov <bp@...en8.de>, 
	Dave Hansen <dave.hansen@...ux.intel.com>
Subject: Re: [PATCH v4 0/4] Relax canonical checks on some arch msrs

On Wed, Oct 30, 2024, Maxim Levitsky wrote:
> On Fri, 2024-09-06 at 18:18 -0400, Maxim Levitsky wrote:
> > Recently we came up upon a failure where likely the guest writes
> > 0xff4547ceb1600000 to MSR_KERNEL_GS_BASE and later on, qemu
> > sets this value via KVM_PUT_MSRS, and is rejected by the
> > kernel, likely due to not being canonical in 4 level paging.
> > 
> > One of the way to trigger this is to make the guest enter SMM,
> > which causes paging to be disabled, which SMM bios re-enables
> > but not the whole 5 level. MSR_KERNEL_GS_BASE on the other
> > hand continues to contain old value.
> > 
> > I did some reverse engineering and to my surprise I found out
> > that both Intel and AMD indeed ignore CR4.LA57 when doing
> > canonical checks on this and other msrs and/or other arch
> > registers (like GDT base) which contain linear addresses.
> > 
> > V2: addressed a very good feedback from Chao Gao. Thanks!
> > 
> > V3: also fix the nested VMX, and also fix the
> > MSR_IA32_SYSENTER_EIP / MSR_IA32_SYSENTER_ESP
> > 
> > V4:
> >   - added PT and PEBS msrs
> >   - corrected emulation of SGDT/SIDT/STR/SLDT instructions
> >   - corrected canonical checks for TLB invalidation instructions
> > 
> > Best regards,
> > 	Maxim Levitsky
> > 
> > Maxim Levitsky (4):
> >   KVM: x86: drop x86.h include from cpuid.h
> >   KVM: x86: implement emul_is_noncanonical_address using
> >     is_noncanonical_address
> >   KVM: x86: model canonical checks more precisely
> >   KVM: nVMX: fix canonical check of vmcs12 HOST_RIP
> > 
> >  arch/x86/kvm/cpuid.h         |  1 -
> >  arch/x86/kvm/emulate.c       | 15 ++++++-----
> >  arch/x86/kvm/kvm_emulate.h   |  5 ++++
> >  arch/x86/kvm/mmu.h           |  1 +
> >  arch/x86/kvm/mmu/mmu.c       |  2 +-
> >  arch/x86/kvm/vmx/hyperv.c    |  1 +
> >  arch/x86/kvm/vmx/nested.c    | 35 +++++++++++++++++---------
> >  arch/x86/kvm/vmx/pmu_intel.c |  2 +-
> >  arch/x86/kvm/vmx/sgx.c       |  5 ++--
> >  arch/x86/kvm/vmx/vmx.c       |  4 +--
> >  arch/x86/kvm/x86.c           | 13 +++++++---
> >  arch/x86/kvm/x86.h           | 49 ++++++++++++++++++++++++++++++++++--
> >  12 files changed, 102 insertions(+), 31 deletions(-)
> > 
> > -- 
> > 2.26.3
> > 
> > 
> 
> Hi,
> A very gentle ping on this patch series.

Heh, good timing, I literally (like, 2 seconds ago) applied this (still need to
test before you'll see a "thank you" email).