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Message-ID: <74458ba4-af0f-4c41-92f5-c6c0cb79e930@linaro.org>
Date: Wed, 30 Oct 2024 08:04:22 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>, alim.akhtar@...sung.com,
James.Bottomley@...senPartnership.com, martin.petersen@...cle.com,
avri.altman@....com, bvanassche@....org, krzk@...nel.org
Cc: andre.draszik@...aro.org, kernel-team@...roid.com,
willmcvicker@...gle.com, linux-scsi@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
ebiggers@...nel.org
Subject: Re: [PATCH v2 01/11] scsi: ufs: exynos: Allow UFS Gear 4
On 10/25/24 2:14 PM, Peter Griffin wrote:
> UFS Gear 4 offers faster speeds, and better power usage so lets
> enable it.
>
> Currently ufshcd_init_host_params() sets UFS_HS_G3 as a default,
> so even if the device supports G4 we end up negotiating down to
> G3.
>
> For SoCs like gs101 which have a UFS major controller version
> of 3 or above advertise Gear 4. This then allows a Gear 4 link
> on Pixel 6.
>
> For earlier controller versions keep the current default behaviour
> of reporting G3.
>
> Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@...aro.org>
some nits/personal preferences below, no need to address them
> ---
> drivers/ufs/host/ufs-exynos.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index 9ec318ef52bf..e25de4b86ac0 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -771,6 +771,21 @@ static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
> exynos_ufs_disable_ov_tm(hba);
> }
>
> +#define UFS_HW_VER_MAJOR_MASK GENMASK(15, 8)
> +
> +static u32 exynos_ufs_get_hs_gear(struct ufs_hba *hba)
> +{
> + u8 major;
> +
> + major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, hba->ufs_version);
> +
> + if (major >= 3)
> + return UFS_HS_G4;
> +
> + /* Default is HS-G3 */
> + return UFS_HS_G3;
> +}
> +
> static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_max_params,
> struct ufs_pa_layer_attr *dev_req_params)
> @@ -787,6 +802,8 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> }
>
> ufshcd_init_host_params(&host_params);
blank line
> + /* This driver only support symmetric gear setting e.g. hs_tx_gear == hs_rx_gear */
> + host_params.hs_tx_gear = host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba);
I find it easier to read if you split inits on their own line:
host_params.hs_tx_gear = exynos_ufs_get_hs_gear(hba);
host_params.hs_rx_gear = exynos_ufs_get_hs_gear(hba);
>
> ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
> if (ret) {
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