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Message-ID: <812499a0-b87e-45e3-b491-5f369b6de5ca@linaro.org>
Date: Wed, 30 Oct 2024 13:10:50 +0200
From: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>
To: Vikram Sharma <quic_vikramsa@...cinc.com>, rfoss@...nel.org,
todor.too@...il.com, bryan.odonoghue@...aro.org, mchehab@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
akapatra@...cinc.com, hariramp@...cinc.com, andersson@...nel.org,
konradybcio@...nel.org, hverkuil-cisco@...all.nl,
cros-qcom-dts-watchers@...omium.org, catalin.marinas@....com, will@...nel.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-media@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, kernel@...cinc.com
Subject: Re: [PATCH v4 1/6] media: dt-bindings: media: camss: Add
qcom,sc7280-camss binding
Hi Vikram,
On 10/30/24 12:53, Vikram Sharma wrote:
> Add bindings for qcom,sc7280-camss to support the camera subsystem
> on the SC7280 platform.
>
> Signed-off-by: Suresh Vankadara <quic_svankada@...cinc.com>
> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@...cinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@...cinc.com>
> ---
<snip>
> +required:
> + - clock-names
> + - clocks
> + - compatible
> + - interconnects
> + - interconnect-names
> + - interrupts
> + - interrupt-names
> + - iommus
> + - power-domains
> + - power-domains-names
> + - reg
> + - reg-names
> + - vdda-phy-supply
> + - vdda-pll-supply
These supplies shall be split into pad specific ones.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,camcc-sc7280.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> + #include <dt-bindings/interconnect/qcom,sc7280.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@...f000 {
Unit address is not the first one from the list of addresses from,
reg values nor it even in the list.
I kindly suggest to sort the list of reg values in address increase
order, this will immediately make visible problems of this type.
> + compatible = "qcom,sc7280-camss";
> +
> + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY0_CLK>,
> + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY1_CLK>,
> + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY2_CLK>,
> + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY3_CLK>,
> + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&clock_camcc CAM_CC_CSIPHY4_CLK>,
> + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CLK>,
> + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CLK>,
> + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CLK>,
> + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>,
> + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>;
> +
> + clock-names = "camnoc_axi",
> + "csi0",
> + "csi1",
> + "csi2",
> + "csi3",
> + "csi4",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "gcc_camera_ahb",
> + "gcc_camera_axi",
> + "soc_ahb",
> + "vfe0_axi",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1_axi",
> + "vfe1",
> + "vfe1_cphy_rx",
> + "vfe2_axi",
> + "vfe2",
> + "vfe2_cphy_rx",
> + "vfe0_lite",
> + "vfe0_lite_cphy_rx",
> + "vfe1_lite",
> + "vfe1_lite_cphy_rx";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>,
> + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>;
> +
> + interconnect-names = "ahb", "hf_0";
> +
> + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + iommus = <&apps_smmu 0x800 0x4e0>;
> +
> + power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
> + <&camcc CAM_CC_IFE_1_GDSC>,
> + <&camcc CAM_CC_IFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + power-domains-names = "ife0", "ife1", "ife2", "top";
> +
> + reg = <0x0 0x0acb3000 0x0 0x1000>,
> + <0x0 0x0acba000 0x0 0x1000>,
> + <0x0 0x0acc1000 0x0 0x1000>,
> + <0x0 0x0acc8000 0x0 0x1000>,
> + <0x0 0x0accf000 0x0 0x1000>,
> + <0x0 0x0ace0000 0x0 0x2000>,
> + <0x0 0x0ace2000 0x0 0x2000>,
> + <0x0 0x0ace4000 0x0 0x2000>,
> + <0x0 0x0ace6000 0x0 0x2000>,
> + <0x0 0x0ace8000 0x0 0x2000>,
> + <0x0 0x0acaf000 0x0 0x4000>,
> + <0x0 0x0acb6000 0x0 0x4000>,
> + <0x0 0x0acbd000 0x0 0x4000>,
> + <0x0 0x0acc4000 0x0 0x4000>,
> + <0x0 0x0accb000 0x0 0x4000>;
> +
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
reg and reg-names properties come right after the compatible property.
> +
> + vdda-phy-supply = <&vreg_l10c_0p88>;
> + vdda-pll-supply = <&vreg_l6b_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
--
Best wishes,
Vladimir
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