linux-kernel - [PATCH v2 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv bitmask

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Message-Id: <20241030-imx-emmc-reset-v2-2-b3a823393974@solid-run.com>
Date: Wed, 30 Oct 2024 14:37:44 +0100
From: Josua Mayer <josua@...id-run.com>
To: Adrian Hunter <adrian.hunter@...el.com>, 
 Haibo Chen <haibo.chen@....com>, Ulf Hansson <ulf.hansson@...aro.org>, 
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>
Cc: Mikhail Anikin <mikhail.anikin@...id-run.com>, 
 Jon Nettleton <jon@...id-run.com>, 
 Yazan Shhady <yazan.shhady@...id-run.com>, 
 Rabeeh Khoury <rabeeh@...id-run.com>, imx@...ts.linux.dev, 
 linux-mmc@...r.kernel.org, s32@....com, 
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 Josua Mayer <josua@...id-run.com>
Subject: [PATCH v2 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl
 dtocv bitmask

NXP ESDHC supports setting data timeout using uSDHCx_SYS_CTRL register
DTOCV bits (bits 16-19).
Currently the driver accesses those bits by 32-bit write using
SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h.
This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C).
The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which
is correct relative to SDHCI_TIMEOUT_CONTROL but not relative to
uSDHCx_SYS_CTRL. The definition carrying control register in its name is
therefore inconsistent.

Update the bitmask definition for bits 16-19 to be correct relative to
control register base.
Update the esdhc_set_timeout function to set timeout value at control
register base, not timeout offset.

This solves a purely cosmetic problem.

Signed-off-by: Josua Mayer <josua@...id-run.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a830d9a9490408d3148b927bf1acc719a13e8975..101feabb24fb41bd10a2e796f4f3f8d4357dc245 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -30,10 +30,10 @@
 #include "sdhci-esdhc.h"
 #include "cqhci.h"
 
-#define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
 #define	ESDHC_CTRL_D3CD			0x08
 #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
 #define ESDHC_SYS_CTRL			0x2c
+#define ESDHC_SYS_CTRL_DTOCV_MASK	GENMASK(19, 16)
 #define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
 /* VENDOR SPEC register */
 #define ESDHC_VENDOR_SPEC		0xc0
@@ -1387,7 +1387,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 
 	/* use maximum timeout counter */
 	esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
-			esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
+			esdhc_is_usdhc(imx_data) ? 0x0F0000 : 0x0E0000,
 			SDHCI_TIMEOUT_CONTROL);
 }
 

-- 
2.43.0