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Message-ID: <c48f70c4-30ed-4df4-b2b3-826be77da799@oss.qualcomm.com>
Date: Thu, 31 Oct 2024 21:09:24 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Jonathan Marek <jonathan@...ek.ca>, linux-arm-msm@...r.kernel.org
Cc: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: x1e80100-crd: add rtc offset to
set rtc time
On 15.10.2024 2:47 AM, Jonathan Marek wrote:
> See commit e67b45582c5e for explanation.
>
> Note: the 0xbc offset is arbitrary, it just needs to not be already in use.
>
> Signed-off-by: Jonathan Marek <jonathan@...ek.ca>
> ---
> arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> index 6dfc85eda3540..eb6b735c41453 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> @@ -1224,6 +1224,17 @@ edp_bl_en: edp-bl-en-state {
> };
> };
>
> +&pmk8550_rtc {
> + nvmem-cells = <&rtc_offset>;
> + nvmem-cell-names = "offset";
> +};
> +
> +&pmk8550_sdam_2 {
> + rtc_offset: rtc-offset@bc {
> + reg = <0xbc 0x4>;
> + };
> +};
Setting random bits in SDAM is a very very very very bad idea
I'll try to get a good spot for the offset internally
Konrad
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