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Message-ID: <bd0b71a2-2e54-43ef-b775-3afbd05fc7de@stanley.mountain>
Date: Thu, 31 Oct 2024 09:55:32 +0300
From: Dan Carpenter <dan.carpenter@...aro.org>
To: oe-kbuild@...ts.linux.dev,
Shengyang Chen <shengyang.chen@...rfivetech.com>
Cc: lkp@...el.com, oe-kbuild-all@...ts.linux.dev,
linux-kernel@...r.kernel.org, Vinod Koul <vkoul@...nel.org>,
Changhuang Liang <changhuang.liang@...rfivetech.com>
Subject: drivers/phy/starfive/phy-jh7110-dphy-tx.c:335 stf_dphy_init() warn:
'dphy->txesc_clk' from clk_prepare_enable() not released on lines: 332.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 0fc810ae3ae110f9e2fcccce80fc8c8d62f97907
commit: d3ab7955330843699cdcc413edd7993923e6c016 phy: starfive: Add mipi dphy tx support
config: riscv-randconfig-r071-20241030 (https://download.01.org/0day-ci/archive/20241031/202410310715.duo3ShR4-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Reported-by: Dan Carpenter <dan.carpenter@...aro.org>
| Closes: https://lore.kernel.org/r/202410310715.duo3ShR4-lkp@intel.com/
smatch warnings:
drivers/phy/starfive/phy-jh7110-dphy-tx.c:335 stf_dphy_init() warn: 'dphy->txesc_clk' from clk_prepare_enable() not released on lines: 332.
vim +335 drivers/phy/starfive/phy-jh7110-dphy-tx.c
d3ab7955330843 Shengyang Chen 2024-04-18 309 static int stf_dphy_init(struct phy *phy)
d3ab7955330843 Shengyang Chen 2024-04-18 310 {
d3ab7955330843 Shengyang Chen 2024-04-18 311 struct stf_dphy *dphy = phy_get_drvdata(phy);
d3ab7955330843 Shengyang Chen 2024-04-18 312 int ret;
d3ab7955330843 Shengyang Chen 2024-04-18 313
d3ab7955330843 Shengyang Chen 2024-04-18 314 stf_dphy_hw_reset(dphy, 1);
d3ab7955330843 Shengyang Chen 2024-04-18 315
d3ab7955330843 Shengyang Chen 2024-04-18 316 writel(FIELD_PREP(STF_DPHY_SCFG_PPI_C_READY_SEL, 0) |
d3ab7955330843 Shengyang Chen 2024-04-18 317 FIELD_PREP(STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL, 0),
d3ab7955330843 Shengyang Chen 2024-04-18 318 dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(48));
d3ab7955330843 Shengyang Chen 2024-04-18 319
d3ab7955330843 Shengyang Chen 2024-04-18 320 writel(FIELD_PREP(STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME, 0x30),
d3ab7955330843 Shengyang Chen 2024-04-18 321 dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(44));
d3ab7955330843 Shengyang Chen 2024-04-18 322
d3ab7955330843 Shengyang Chen 2024-04-18 323 ret = clk_prepare_enable(dphy->txesc_clk);
d3ab7955330843 Shengyang Chen 2024-04-18 324 if (ret) {
d3ab7955330843 Shengyang Chen 2024-04-18 325 dev_err(dphy->dev, "Failed to prepare/enable txesc_clk\n");
d3ab7955330843 Shengyang Chen 2024-04-18 326 return ret;
d3ab7955330843 Shengyang Chen 2024-04-18 327 }
d3ab7955330843 Shengyang Chen 2024-04-18 328
d3ab7955330843 Shengyang Chen 2024-04-18 329 ret = reset_control_deassert(dphy->sys_rst);
d3ab7955330843 Shengyang Chen 2024-04-18 330 if (ret) {
d3ab7955330843 Shengyang Chen 2024-04-18 331 dev_err(dphy->dev, "Failed to deassert sys_rst\n");
clk_disable_unprepare(dphy->txesc_clk);?
d3ab7955330843 Shengyang Chen 2024-04-18 332 return ret;
d3ab7955330843 Shengyang Chen 2024-04-18 333 }
d3ab7955330843 Shengyang Chen 2024-04-18 334
d3ab7955330843 Shengyang Chen 2024-04-18 @335 return 0;
d3ab7955330843 Shengyang Chen 2024-04-18 336 }
--
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https://github.com/intel/lkp-tests/wiki
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