linux-kernel - [PATCH v2 01/13] arm64: dts: allwinner: A100: Add PMU mode

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Message-ID: <20241031070232.1793078-2-masterr3c0rd@epochal.quest>
Date: Thu, 31 Oct 2024 04:02:14 -0300
From: Cody Eksal <masterr3c0rd@...chal.quest>
To: Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chen-Yu Tsai <wens@...e.org>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Samuel Holland <samuel@...lland.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Maxime Ripard <mripard@...nel.org>,
	Michael Turquette <mturquette@...libre.com>,
	Nishanth Menon <nm@...com>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	Stephen Boyd <sboyd@...nel.org>,
	Vinod Koul <vkoul@...nel.org>,
	Viresh Kumar <vireshk@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>,
	Yangtao Li <tiny.windzz@...il.com>,
	Parthiban <parthiban@...umiz.com>,
	Andre Przywara <andre.przywara@....com>,
	Cody Eksal <masterr3c0rd@...chal.quest>,
	devicetree@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-sunxi@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: [PATCH v2 01/13] arm64: dts: allwinner: A100: Add PMU mode

From: Yangtao Li <frank@...winnertech.com>

Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.

Signed-off-by: Yangtao Li <frank@...winnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@....com>
Signed-off-by: Cody Eksal <masterr3c0rd@...chal.quest>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index a3dccf193765..1eca7c220ede 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.47.0