| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20241031080655.3879139-1-hongxing.zhu@nxp.com> Date: Thu, 31 Oct 2024 16:06:45 +0800 From: Richard Zhu <hongxing.zhu@....com> To: l.stach@...gutronix.de, bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com, manivannan.sadhasivam@...aro.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, shawnguo@...nel.org, frank.li@....com, s.hauer@...gutronix.de, festevam@...il.com Cc: imx@...ts.linux.dev, kernel@...gutronix.de, linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v5 0/10] A bunch of changes to refine i.MX PCIe driver A bunch of changes to refine i.MX PCIe driver. - Add ref clock gate for i.MX95 PCIe. The changes of clock part are here [1], and had been applied by Abel. [1] https://lkml.org/lkml/2024/10/15/390 - Clean i.MX PCIe driver by removing useless codes. Patch #3 depends on dts changes. And the dts changes had been applied by Shawn, there is no dependecy now. - Make core reset and enable_ref_clk symmetric for i.MX PCIe driver. - Use dwc common suspend resume method, and enable i.MX8MQ, i.MX8Q and i.MX95 PCIe PM supports. v5 changes: Thanks for Manivannan's review. - To avoid the DT compatibility on i.MX95, let to fetch i.MX95 PCIe clocks be optinal in driver. - Add Fixes tags into #5 and #6 patches. - Split the clean up codes into #7. - Update the commit message in #10, and #8 "PCI: imx6: Use dwc common suspend resume method" patches. v4 changes: It's my fault that I missing Manivannan in the reviewer list. I'm sorry about that. - Rebase to v6.12-rc3, and resolve the dtsi conflictions. Add Manivannan into reviewer list. v3 changes: - Update EP binding refer to comments provided by Krzysztof Kozlowski. Thanks. v2 changes: - Add the reasons why one more clock is added for i.MX95 PCIe in patch #1. - Add the "Reviewed-by: Frank Li <Frank.Li@....com>" into patch #2, #4, #5, #6, #8 and #9. [PATCH v5 01/10] dt-bindings: imx6q-pcie: Add ref clock for i.MX95 [PATCH v5 02/10] PCI: imx6: Add ref clock for i.MX95 PCIe [PATCH v5 03/10] PCI: imx6: Fetch dbi2 and iATU base addesses from DT [PATCH v5 04/10] PCI: imx6: Correct controller_id generation logic [PATCH v5 05/10] PCI: imx6: Make core reset assertion deassertion [PATCH v5 06/10] PCI: imx6: Fix the missing reference clock disable [PATCH v5 07/10] PCI: imx6: Clean up codes by removing [PATCH v5 08/10] PCI: imx6: Use dwc common suspend resume method [PATCH v5 09/10] PCI: imx6: Add i.MX8MQ i.MX8Q and i.MX95 PCIe PM [PATCH v5 10/10] arm64: dts: imx95: Add ref clock for i.MX95 PCIe Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml | 4 +- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 1 + Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++-- arch/arm64/boot/dts/freescale/imx95.dtsi | 18 ++++++-- drivers/pci/controller/dwc/pci-imx6.c | 174 +++++++++++++++++++++++++++++----------------------------------------------- 5 files changed, 104 insertions(+), 118 deletions(-)
Powered by blists - more mailing lists