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Message-Id: <20241031080655.3879139-3-hongxing.zhu@nxp.com>
Date: Thu, 31 Oct 2024 16:06:47 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: l.stach@...gutronix.de,
bhelgaas@...gle.com,
lpieralisi@...nel.org,
kw@...ux.com,
manivannan.sadhasivam@...aro.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
shawnguo@...nel.org,
frank.li@....com,
s.hauer@...gutronix.de,
festevam@...il.com
Cc: imx@...ts.linux.dev,
kernel@...gutronix.de,
linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Richard Zhu <hongxing.zhu@....com>,
Frank Li <Frank.Li@....com>
Subject: [PATCH v5 02/10] PCI: imx6: Add ref clock for i.MX95 PCIe
Add "ref" clock to enable reference clock. To avoid the DT
compatibility, i.MX95 REF clock might be optional. Replace the
devm_clk_bulk_get() by devm_clk_bulk_get_optional() to fetch
i.MX95 PCIe clocks in driver.
If use external clock, ref clock should point to external reference.
If use internal clock, CREF_EN in LAST_TO_REG controls reference output,
which implement in drivers/clk/imx/clk-imx95-blk-ctl.c.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
Reviewed-by: Frank Li <Frank.Li@....com>
---
drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 808d1f105417..73cb69ba8933 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -82,6 +82,7 @@ enum imx_pcie_variants {
#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7)
#define IMX_PCIE_FLAG_CPU_ADDR_FIXUP BIT(8)
+#define IMX_PCIE_FLAG_CLOCKS_OPTIONAL BIT(9)
#define imx_check_flag(pci, val) (pci->drvdata->flags & val)
@@ -1330,7 +1331,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i];
/* Fetch clocks */
- ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_CLOCKS_OPTIONAL))
+ ret = devm_clk_bulk_get_optional(dev, imx_pcie->drvdata->clks_cnt,
+ imx_pcie->clks);
+ else
+ ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt,
+ imx_pcie->clks);
if (ret)
return ret;
@@ -1480,6 +1486,8 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"};
+static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"};
+static const char * const imx95_ext_osc_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
static const struct imx_pcie_drvdata drvdata[] = {
[IMX6Q] = {
@@ -1592,9 +1600,10 @@ static const struct imx_pcie_drvdata drvdata[] = {
},
[IMX95] = {
.variant = IMX95,
- .flags = IMX_PCIE_FLAG_HAS_SERDES,
- .clk_names = imx8mq_clks,
- .clks_cnt = ARRAY_SIZE(imx8mq_clks),
+ .flags = IMX_PCIE_FLAG_HAS_SERDES |
+ IMX_PCIE_FLAG_CLOCKS_OPTIONAL,
+ .clk_names = imx95_clks,
+ .clks_cnt = ARRAY_SIZE(imx95_clks),
.ltssm_off = IMX95_PE0_GEN_CTRL_3,
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
--
2.37.1
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