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Message-ID: <f5c6e45c-a224-42b6-a479-aa90fd6aabed@microchip.com>
Date: Thu, 31 Oct 2024 10:07:52 +0000
From: <Valentina.FernandezAlanis@...rochip.com>
To: <robh@...nel.org>
CC: <paul.walmsley@...ive.com>, <palmer@...belt.com>, <aou@...s.berkeley.edu>,
<peterlin@...estech.com>, <Conor.Dooley@...rochip.com>,
<conor+dt@...nel.org>, <ycliang@...estech.com>, <dminus@...estech.com>,
<prabhakar.mahadev-lad.rj@...renesas.com>, <jassisinghbrar@...il.com>,
<krzk+dt@...nel.org>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 2/3] dt-bindings: mailbox: add binding for Microchip
IPC mailbox controller
On 29/10/2024 12:48, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Fri, Oct 25, 2024 at 01:51:09PM +0100, Valentina Fernandez wrote:
>> Add a dt-binding for the Microchip Inter-Processor Communication (IPC)
>> mailbox controller.
>>
>> Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@...rochip.com>
>> ---
>> .../bindings/mailbox/microchip,sbi-ipc.yaml | 108 ++++++++++++++++++
>> 1 file changed, 108 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml
>> new file mode 100644
>> index 000000000000..90a7932118b5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microchip Inter-processor communication (IPC) mailbox controller
>> +
>> +maintainers:
>> + - Valentina Fernandez <valentina.fernandezalanis@...rochip.com>
>> +
>> +description:
>
> You need '>' and blank line in between each paragraph if you want the
> paragraphs maintained.
>
> Elsewhere too.
>
>> + The Microchip Inter-processor Communication (IPC) facilitates
>> + message passing between processors using an interrupt signaling
>> + mechanism.
>> + This SBI interface is compatible with the Mi-V Inter-hart
>> + Communication (IHC) IP.
>> + The microchip,sbi-ipc compatible string is inteded for use by software
>> + running in supervisor privileged mode (s-mode). The SoC-specific
>> + compatibles are inteded for use by the SBI implementation in machine
>
> intended
>
>> + mode (m-mode).
>
> This per compatible information should be with the compatibles.
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - microchip,sbi-ipc
>> + - microchip,miv-ihc-rtl-v2
>
> To add per compatible descriptions, you can do:
>
> oneOf:
> - const:
> description: ...
> - const:
> description: ...
>
>
>
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + minItems: 1
>> + maxItems: 5
>> +
>> + interrupt-names:
>> + minItems: 1
>> + maxItems: 5
>> + items:
>> + pattern: "^hart-[0-5]+$"
>
> Is the numbering always contiguous (e.g. not "hart-0, hart-3")? If so,
> drop the names. A name matching the index of the entry is not useful.
Numbering can be non-contiguous based on the user's AMP configuration
(e.g., 'hart-3', 'hart-4', 'hart-1').
Thanks for the rest of the feedback, I'll implement those changes in v3.
>
>> +
>> + "#mbox-cells":
>> + description:
>> + For the SBI "device", the cell represents the global "logical" channel IDs.
>> + The meaning of channel IDs are platform firmware dependent. The
>> + SoC-specific compatibles are intended for use by the SBI implementation,
>> + rather than s-mode software. There the cell would represent the physical
>> + channel and do not vary depending on platform firmware.
>> + const: 1
>> +
>> + microchip,ihc-chan-disabled-mask:
>> + description:
>> + Represents the enable/disable state of the bi-directional IHC channels
>> + within the MIV-IHC IP configuration. The mask is a 16-bit value, but only
>> + the first 15 bits are utilized.Each of the bits corresponds to
>> + one of the 15 IHC channels.
>> + A bit set to '1' indicates that the corresponding channel is disabled,
>> + and any read or write operations to that channel will return zero.
>> + A bit set to '0' indicates that the corresponding channel is enabled
>> + and will be accessible through its dedicated address range registers.
>> + The remaining bit of the 16-bit mask is reserved and should be ignored.
>> + The actual enable/disable state of each channel is determined by the
>> + IP block’s configuration.
>> + $ref: /schemas/types.yaml#/definitions/uint16
>> + default: 0
>> +
>> +required:
>> + - compatible
>> + - interrupts
>> + - interrupt-names
>> + - "#mbox-cells"
>> +
>> +additionalProperties: false
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: microchip,sbi-ipc
>> + then:
>> + properties:
>> + reg: false
>> + microchip,ihc-chan-disabled-mask: false
>> + else:
>> + required:
>> + - reg
>> + - microchip,ihc-chan-disabled-mask
>> +
>> +examples:
>> + - |
>> + mailbox {
>> + compatible = "microchip,sbi-ipc";
>> + interrupt-parent = <&plic>;
>> + interrupts = <180>, <179>, <178>;
>> + interrupt-names = "hart-1", "hart-2", "hart-3";
>> + #mbox-cells = <1>;
>> + };
>> + - |
>> + mailbox@...00000 {
>> + compatible = "microchip,miv-ihc-rtl-v2";
>> + microchip,ihc-chan-disabled-mask= /bits/ 16 <0>;
>
> Incorrect formatting around the '='.
>
>> + reg = <0x50000000 0x1C000>;
>> + interrupt-parent = <&plic>;
>> + interrupts = <180>, <179>, <178>;
>> + interrupt-names = "hart-1", "hart-2", "hart-3";
>> + #mbox-cells = <1>;
>> + };
>> --
>> 2.34.1
>>
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