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Message-Id: <20241031123643.272111-1-changhuang.liang@starfivetech.com>
Date: Thu, 31 Oct 2024 05:36:43 -0700
From: Changhuang Liang <changhuang.liang@...rfivetech.com>
To: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Maxime Ripard <mripard@...nel.org>
Cc: Changhuang Liang <changhuang.liang@...rfivetech.com>,
linux-phy@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [RFC PATCH] phy: dphy: Fix Unit Interval(UI) calculation formula
ALIGN() expects its second argument to be a power of 2, but in the
context, the hs_clk_rate will not satisfy this condition in most
cases. This may lead to unknown results in the UI calculation.
So, let fix the UI calculation formula.
Fixes: dddc97e82303 ("phy: dphy: Add configuration helpers")
Signed-off-by: Changhuang Liang <changhuang.liang@...rfivetech.com>
---
Hi, Maxime
This patch may require your careful review. I have no environmental test
so there is no guarantee of any effect.
This UI calculation is a reference to your patch:
https://lore.kernel.org/all/aa491b814100a670ad16b646765005efbdae05d9.1536138624.git-series.maxime.ripard@bootlin.com/
Best Regards,
Changhuang
drivers/phy/phy-core-mipi-dphy.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
index f4956a417a47..c7712e594dbf 100644
--- a/drivers/phy/phy-core-mipi-dphy.c
+++ b/drivers/phy/phy-core-mipi-dphy.c
@@ -33,8 +33,7 @@ static int phy_mipi_dphy_calc_config(unsigned long pixel_clock,
do_div(hs_clk_rate, lanes);
}
- ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
- do_div(ui, hs_clk_rate);
+ ui = DIV_ROUND_UP(PSEC_PER_SEC, hs_clk_rate);
cfg->clk_miss = 0;
cfg->clk_post = 60000 + 52 * ui;
@@ -111,8 +110,7 @@ int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
if (!cfg)
return -EINVAL;
- ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
- do_div(ui, cfg->hs_clk_rate);
+ ui = DIV_ROUND_UP(PSEC_PER_SEC, cfg->hs_clk_rate);
if (cfg->clk_miss > 60000)
return -EINVAL;
--
2.25.1
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