linux-kernel - RE: [PATCH v2 1/2] mmc: host: sdhci-esdhc-imx: implement emmc hardware reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <DU0PR04MB94960B8DC51D38061FAE880D90552@DU0PR04MB9496.eurprd04.prod.outlook.com>
Date: Thu, 31 Oct 2024 01:39:02 +0000
From: Bough Chen <haibo.chen@....com>
To: Josua Mayer <josua@...id-run.com>, Adrian Hunter
	<adrian.hunter@...el.com>, Ulf Hansson <ulf.hansson@...aro.org>, Shawn Guo
	<shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, Pengutronix
 Kernel Team <kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>
CC: Mikhail Anikin <mikhail.anikin@...id-run.com>, Jon Nettleton
	<jon@...id-run.com>, yazan.shhady <yazan.shhady@...id-run.com>, Rabeeh Khoury
	<rabeeh@...id-run.com>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
	"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, dl-S32
	<S32@....com>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 1/2] mmc: host: sdhci-esdhc-imx: implement emmc
 hardware reset

> -----Original Message-----
> From: Josua Mayer <josua@...id-run.com>
> Sent: 2024年10月30日 21:38
> To: Adrian Hunter <adrian.hunter@...el.com>; Bough Chen
> <haibo.chen@....com>; Ulf Hansson <ulf.hansson@...aro.org>; Shawn Guo
> <shawnguo@...nel.org>; Sascha Hauer <s.hauer@...gutronix.de>;
> Pengutronix Kernel Team <kernel@...gutronix.de>; Fabio Estevam
> <festevam@...il.com>
> Cc: Mikhail Anikin <mikhail.anikin@...id-run.com>; Jon Nettleton
> <jon@...id-run.com>; yazan.shhady <yazan.shhady@...id-run.com>; Rabeeh
> Khoury <rabeeh@...id-run.com>; imx@...ts.linux.dev;
> linux-mmc@...r.kernel.org; dl-S32 <S32@....com>;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Josua
> Mayer <josua@...id-run.com>
> Subject: [PATCH v2 1/2] mmc: host: sdhci-esdhc-imx: implement emmc
> hardware reset
> 
> NXP ESDHC supports control of native emmc reset signal when pinmux is set
> accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit.
> Documentation is available in NXP i.MX6Q Reference Manual.
> 
> Implement the hw_reset function in sdhci_ops asserting reset for at least 1us
> and waiting at least 200us after deassertion.
> Lower bounds are based on:
> JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159.
> Upper bounds are chosen allowing flexibility to the scheduler.
> 
> Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is
> still accessible after boot:
> - eMMC extcsd has RST_N_FUNCTION=0x01
> - sdhc node has cap-mmc-hw-reset
> - pinmux set for EMMC0_RESET_B
> - Linux v5.15
> 
> Signed-off-by: Josua Mayer <josua@...id-run.com>
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index
> 8f0bc6dca2b0402fd2a0695903cf261a5b4e19dc..a830d9a9490408d3148b927bf
> 1acc719a13e8975 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -33,6 +33,8 @@
>  #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
>  #define	ESDHC_CTRL_D3CD			0x08
>  #define ESDHC_BURST_LEN_EN_INCR		(1 << 27)
> +#define ESDHC_SYS_CTRL			0x2c

No need this definition, already done in drivers/mmc/host/sdhci-esdhc.h

#define ESDHC_SYSTEM_CONTROL            0x2c

Regards
Haibo Chen


> +#define ESDHC_SYS_CTRL_IPP_RST_N	BIT(23)
>  /* VENDOR SPEC register */
>  #define ESDHC_VENDOR_SPEC		0xc0
>  #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK	(1 << 1)
> @@ -1402,6 +1404,17 @@ static u32 esdhc_cqhci_irq(struct sdhci_host *host,
> u32 intmask)
>  	return 0;
>  }
> 
> +static void esdhc_hw_reset(struct sdhci_host *host) {
> +	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYS_CTRL);
> +	/* eMMC spec requires minimum 1us, here delay between 1-10us */
> +	usleep_range(1, 10);
> +	esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N,
> +			ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYS_CTRL);
> +	/* eMMC spec requires minimum 200us, here delay between 200-300us */
> +	usleep_range(200, 300);
> +}
> +
>  static struct sdhci_ops sdhci_esdhc_ops = {
>  	.read_l = esdhc_readl_le,
>  	.read_w = esdhc_readw_le,
> @@ -1420,6 +1433,7 @@ static struct sdhci_ops sdhci_esdhc_ops = {
>  	.reset = esdhc_reset,
>  	.irq = esdhc_cqhci_irq,
>  	.dump_vendor_regs = esdhc_dump_debug_regs,
> +	.hw_reset = esdhc_hw_reset,
>  };
> 
>  static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
> 
> --
> 2.43.0