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Message-ID: <0782c956-361b-4109-a8a1-58b8ad396e0b@quicinc.com>
Date: Fri, 1 Nov 2024 11:14:25 -0700
From: Melody Olvera <quic_molvera@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Bjorn Andersson
<andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Satya Durga Srinivasu Prabhala
<quic_satyap@...cinc.com>,
Srinivas Kandagatla
<srinivas.kandagatla@...aro.org>
Subject: Re: [PATCH 1/4] arm64: dts: qcom: sm8750: Add IPCC, SMP2P, AOSS and
ADSP
On 11/1/2024 10:19 AM, Krzysztof Kozlowski wrote:
> Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc
> PAS loader (compatible with SM8550).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++++++++++
> 1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 98ab82caa007ee63c395a3ce0f517e2bbeb0aecb..eb826b154dcb2d8165426ba2225548efd7547da8 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
[...]
>
> @@ -538,6 +566,17 @@ gcc: clock-controller@...000 {
> #power-domain-cells = <1>;
> };
>
> + ipcc: mailbox@...000 {
> + compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
> + reg = <0 0x00406000 0 0x1000>;
nit: unsure, but should thse be 0x0?
> +
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + #mbox-cells = <2>;
> + };
> +
> gpi_dma2: dma-controller@...000 {
> compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
> reg = <0x0 0x00800000 0x0 0x60000>;
> @@ -1975,6 +2014,19 @@ pdc: interrupt-controller@...0000 {
> interrupt-controller;
> };
>
> + aoss_qmp: power-management@...0000 {
> + compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp";
> + reg = <0 0x0c300000 0 0x400>;
Same as above.
> +
> + interrupt-parent = <&ipcc>;
> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + #clock-cells = <0>;
> + };
> +
> spmi_bus: spmi@...0000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x0 0xc400000 0x0 0x3000>,
> @@ -2884,6 +2936,94 @@ gem_noc: interconnect@...00000 {
> #interconnect-cells = <2>;
> };
>
> + remoteproc_adsp: remoteproc@...00000 {
> + compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
> + reg = <0 0x30000000 0 0x100>;
Same as above.
> +
> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
[...]
Otherwise, LGTM.
Reviewed-by: Melody Olvera <quic_molvera@...cinc.com>
Thanks,
Melody
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