lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <900d2449-ff88-45ea-9b29-da145541d42b@lunn.ch>
Date: Sat, 2 Nov 2024 18:03:07 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Diogo Silva <diogompaissilva@...il.com>
Cc: hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org, marex@...x.de,
	tolvupostur@...il.com
Subject: Re: [PATCH] net: phy: ti: add PHY_RST_AFTER_CLK_EN flag

On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> From: Diogo Silva <diogompaissilva@...il.com>
> 
> DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
> toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> make sure that this indication is respected.

Do you have the datasheets for the other three devices this driver
supports? Do they all require this flag?

	Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ