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Message-ID: <6e5298c0-eded-4fd2-8ce6-52d4239da53c@lunn.ch>
Date: Sun, 3 Nov 2024 16:20:33 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Diogo Silva <diogompaissilva@...il.com>
Cc: hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
	edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org, marex@...x.de,
	tolvupostur@...il.com
Subject: Re: [PATCH] net: phy: ti: add PHY_RST_AFTER_CLK_EN flag

On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> From: Diogo Silva <diogompaissilva@...il.com>
> 
> DP83848	datasheet (section 4.7.2) indicates that the reset pin should be
> toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> make sure that this indication is respected.
> 
> In my experience not having this flag enabled would lead to, on some
> boots, the wrong MII mode being selected if the PHY was initialized on
> the bootloader and was receiving data during Linux boot.
> 
> Signed-off-by: Diogo Silva <diogompaissilva@...il.com>

This should be merged to net.

Fixes: 34e45ad9378c ("net: phy: dp83848: Add TI DP83848 Ethernet PHY")
Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew

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