linux-kernel - Re: [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed and width

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Message-ID: <20241104170005.GA4055778@rocinante>
Date: Tue, 5 Nov 2024 02:00:05 +0900
From: Krzysztof Wilczyński <kw@...ux.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-pci@...r.kernel.org, ryder.lee@...iatek.com,
	jianjun.wang@...iatek.com, lpieralisi@...nel.org, robh@...nel.org,
	bhelgaas@...gle.com, matthias.bgg@...il.com,
	linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, kernel@...labora.com,
	fshao@...omium.org
Subject: Re: [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed
 and width

Hello,

> Changes in v4:
>  - Addressed comments from Jianjun Wang's review on v3
> 
> Changes in v3:
>  - Addressed comments from Fei Shao's review on v2
> 
> Changes in v2:
>  - Rebased on next-20240917
> 
> This series adds support for limiting the PCI-Express link speed
> (or PCIe gen restriction) and link width (number of lanes) in the
> pcie-mediatek-gen3 driver.
> 
> The maximum supported pcie gen is read from the controller itself,
> so defining a max gen through platform data for each SoC is avoided.
> 
> Both are done by adding support for the standard devicetree properties
> `max-link-speed` and `num-lanes`.
> 
> Please note that changing the bindings is not required, as those do
> already allow specifying those properties for this controller.

Applied to controller/mediatek, thank you!

[01/02] PCI: mediatek-gen3: Add support for setting max-link-speed limit
        https://git.kernel.org/pci/pci/c/ade7da14954a

[02/02] PCI: mediatek-gen3: Add support for restricting link width
        https://git.kernel.org/pci/pci/c/6e73c5898973

	Krzysztof