linux-kernel - [PATCH v1 3/3] arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

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Message-ID: <20241104073840.3686674-4-quic_varada@quicinc.com>
Date: Mon, 4 Nov 2024 13:08:40 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: <andersson@...nel.org>, <konradybcio@...nel.org>, <conor@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
CC: Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: [PATCH v1 3/3] arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on
IPQ5424 SoCs.

Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 76af0d87e9a8..497df93acf47 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -137,6 +137,13 @@ soc@0 {
 		#size-cells = <2>;
 		ranges = <0 0 0 0 0x10 0>;
 
+		system-cache-controller@...000 {
+			compatible = "qcom,ipq5424-llcc";
+			reg = <0 0x00800000 0 0x200000>;
+			reg-names = "llcc0_base";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		tlmm: pinctrl@...0000 {
 			compatible = "qcom,ipq5424-tlmm";
 			reg = <0 0x01000000 0 0x300000>;
-- 
2.34.1