linux-kernel - Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting link width

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Message-ID: <9351c903-8141-4721-a352-776215afbfa1@collabora.com>
Date: Mon, 4 Nov 2024 11:43:52 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Jianjun Wang (王建军) <Jianjun.Wang@...iatek.com>,
 "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
 "kernel@...labora.com" <kernel@...labora.com>,
 "robh@...nel.org" <robh@...nel.org>, "kw@...ux.com" <kw@...ux.com>,
 "linux-arm-kernel@...ts.infradead.org"
 <linux-arm-kernel@...ts.infradead.org>,
 "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
 "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
 "lpieralisi@...nel.org" <lpieralisi@...nel.org>,
 Ryder Lee <Ryder.Lee@...iatek.com>, "fshao@...omium.org" <fshao@...omium.org>
Subject: Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting
 link width

Il 04/11/24 09:56, Jianjun Wang (王建军) ha scritto:
> Hi Angelo,
> 
> Thanks for your patch.
> 
> On Wed, 2024-09-18 at 10:13 +0200, AngeloGioacchino Del Regno wrote:
>> Add support for restricting the port's link width by specifying
>> the num-lanes devicetree property in the PCIe node.
>>
>> The setting is done in the GEN_SETTINGS register (in the driver
>> named as PCIE_SETTING_REG), where each set bit in [11:8] activates
>> a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
>>
>> Signed-off-by: AngeloGioacchino Del Regno <
>> angelogioacchino.delregno@...labora.com>
>> ---
>>   drivers/pci/controller/pcie-mediatek-gen3.c | 20
>> ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
>> b/drivers/pci/controller/pcie-mediatek-gen3.c
>> index 8d4b045633da..8dd2e5135b01 100644
>> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
>> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
>> @@ -32,6 +32,7 @@
>>   #define PCIE_BASE_CFG_SPEED		GENMASK(15, 8)
>>   
>>   #define PCIE_SETTING_REG		0x80
>> +#define PCIE_SETTING_LINK_WIDTH		GENMASK(11, 8)
>>   #define PCIE_SETTING_GEN_SUPPORT	GENMASK(14, 12)
>>   #define PCIE_PCI_IDS_1			0x9c
>>   #define PCI_CLASS(class)		(class << 8)
>> @@ -168,6 +169,7 @@ struct mtk_msi_set {
>>    * @clks: PCIe clocks
>>    * @num_clks: PCIe clocks count for this port
>>    * @max_link_speed: Maximum link speed (PCIe Gen) for this port
>> + * @num_lanes: Number of PCIe lanes for this port
>>    * @irq: PCIe controller interrupt number
>>    * @saved_irq_state: IRQ enable state saved at suspend time
>>    * @irq_lock: lock protecting IRQ register access
>> @@ -189,6 +191,7 @@ struct mtk_gen3_pcie {
>>   	struct clk_bulk_data *clks;
>>   	int num_clks;
>>   	u8 max_link_speed;
>> +	u8 num_lanes;
>>   
>>   	int irq;
>>   	u32 saved_irq_state;
>> @@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct
>> mtk_gen3_pcie *pcie)
>>   			val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,
>>   					  GENMASK(pcie->max_link_speed
>> - 2, 0));
>>   	}
>> +	if (pcie->num_lanes) {
>> +		val &= ~PCIE_SETTING_LINK_WIDTH;
>> +
>> +		/* Zero means one lane, each bit activates x2/x4/x8/x16
>> */
>> +		if (pcie->num_lanes > 1)
>> +			val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,
>> +					  GENMASK(pcie->num_lanes >> 1,
>> 0));
> 
> It should be GENMASK(fls(pcie->num_lanes) - 2, 0).
> 

You're right in that there's a mistake in that one, and I see it now,
but I don't get why this should be "fls(...) - 2".

The datasheet says that "LinkWidths" is

Bit 8 = x2 supported
Bit 9 = x4 supported
Bit 10 = x8 supported
Bit 11 = x16 supported

pcie->num_lanes can be set to either 2, 4, 8 or 16.

2>>2 = 0   -> fls(0) == 0 (after field_prep/genmask: bit 8)
4>>2 = 1   -> fls(1) == 1 (after field_prep/genmask: bit 9 to 8)
8>>2 = 2   -> fls(2) == 2 (after field_prep/genmask: bit 10 to 8)
16>>2 = 4  -> fls(4) == 3 (after field_prep/genmask: bit 11 to 8)

So, this should be
	GENMASK(fls(pcie->num_lanes >> 2), 0)

Right? :-)

In which case, should I send a new version, or can you fix that while
applying? I'd really appreciate the latter due to lack of time.

Cheers,
Angelo

> Thanks.
> 
>> +	};
>>   	writel_relaxed(val, pcie->base + PCIE_SETTING_REG);
>>   
>>   	/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
>> @@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct
>> mtk_gen3_pcie *pcie)
>>   	struct device *dev = pcie->dev;
>>   	struct platform_device *pdev = to_platform_device(dev);
>>   	struct resource *regs;
>> +	u32 num_lanes;
>>   
>>   	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> "pcie-mac");
>>   	if (!regs)
>> @@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct
>> mtk_gen3_pcie *pcie)
>>   		return pcie->num_clks;
>>   	}
>>   
>> +	ret = of_property_read_u32(dev->of_node, "num-lanes",
>> &num_lanes);
>> +	if (ret == 0) {
>> +		if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1
>> && num_lanes % 2))
>> +			dev_warn(dev, "Invalid num-lanes, using
>> controller defaults\n");
>> +		else
>> +			pcie->num_lanes = num_lanes;
>> +	}
>> +
>>   	return 0;
>>   }
>>