linux-kernel - Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

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Message-ID: <CAMj1kXEPM+4B4xTThOejMZ5bLHcwzNYbW333ZZu1YFJGy5johg@mail.gmail.com>
Date: Mon, 4 Nov 2024 12:52:25 +0100
From: Ard Biesheuvel <ardb@...nel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Linus Walleij <linus.walleij@...aro.org>
Cc: Sudeep Holla <sudeep.holla@....com>, Russell King <linux@...linux.org.uk>, 
	linux-arm-kernel@...ts.infradead.org, linux-arm-msm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Bjorn Andersson <andersson@...nel.org>, 
	Konrad Dybcio <konradybcio@...nel.org>, Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

(cc Linus)

On Mon, 4 Nov 2024 at 12:51, Dmitry Baryshkov
<dmitry.baryshkov@...aro.org> wrote:
>
> On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote:
> > Follow the ARM64 platform and implement simple cache information driver.
> > As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> > limited to the ARMv7 / ARMv7M, providing simple fallback or just
> > returning -EOPNOTSUPP in case of older platforms.
> >
> > In theory we should be able to skip CLIDR reading and assume that Dcache
> > and Icache (or unified L1 cache) always exist if CTR is supported and
> > returns sensible value. However I think this better be handled by the
> > maintainers of corresponding platforms.
> >
> > Other than just providing information to the userspace, this patchset is
> > required in order to implement L2 cache driver (and in the end CPU
> > frequency scaling) on ARMv7-based Qualcomm devices.
>
> Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for
> this for several months. Is there a chance to hear anything? I'd really
> like to scratch this off my 'pending' list.
>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> > ---
> > Changes in v2:
> > - Handle cores like ARM1176, which have cpu_architecture() ==
> >   CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR
> >   register (because they are ARMv6) (Arnd).
> > - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org
>
> --
> With best wishes
> Dmitry