linux-kernel - [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed and width

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Message-ID: <20241104114935.172908-1-angelogioacchino.delregno@collabora.com>
Date: Mon,  4 Nov 2024 12:49:33 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: linux-pci@...r.kernel.org
Cc: ryder.lee@...iatek.com,
	jianjun.wang@...iatek.com,
	lpieralisi@...nel.org,
	kw@...ux.com,
	robh@...nel.org,
	bhelgaas@...gle.com,
	matthias.bgg@...il.com,
	angelogioacchino.delregno@...labora.com,
	linux-mediatek@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	kernel@...labora.com,
	fshao@...omium.org
Subject: [PATCH v4 0/2] PCI: mediatek-gen3: Support limiting link speed and width

Changes in v4:
 - Addressed comments from Jianjun Wang's review on v3

Changes in v3:
 - Addressed comments from Fei Shao's review on v2

Changes in v2:
 - Rebased on next-20240917

This series adds support for limiting the PCI-Express link speed
(or PCIe gen restriction) and link width (number of lanes) in the
pcie-mediatek-gen3 driver.

The maximum supported pcie gen is read from the controller itself,
so defining a max gen through platform data for each SoC is avoided.

Both are done by adding support for the standard devicetree properties
`max-link-speed` and `num-lanes`.

Please note that changing the bindings is not required, as those do
already allow specifying those properties for this controller.

AngeloGioacchino Del Regno (2):
  PCI: mediatek-gen3: Add support for setting max-link-speed limit
  PCI: mediatek-gen3: Add support for restricting link width

 drivers/pci/controller/pcie-mediatek-gen3.c | 75 ++++++++++++++++++++-
 1 file changed, 73 insertions(+), 2 deletions(-)

-- 
2.46.1