linux-kernel - Re: [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension

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Message-ID: <20241104-number-recall-85e044c9b72d@spud>
Date: Mon, 4 Nov 2024 12:07:49 +0000
From: Conor Dooley <conor@...nel.org>
To: Clément Léger <cleger@...osinc.com>
Cc: Inochi Amaoto <inochiama@...il.com>, Jonathan Corbet <corbet@....net>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Evan Green <evan@...osinc.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Andy Chiu <andybnac@...il.com>, Xiao Wang <xiao.w.wang@...el.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	linux-doc@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA
 extension

On Mon, Nov 04, 2024 at 10:15:56AM +0100, Clément Léger wrote:
> 
> 
> On 03/11/2024 08:49, Inochi Amaoto wrote:
> > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which
> > were ratified in 4dc23d62 ("Added Chapter title to BF16") of
> > the riscv-isa-manual.
> > 
> > Signed-off-by: Inochi Amaoto <inochiama@...il.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h | 3 +++
> >  arch/riscv/kernel/cpufeature.c | 3 +++
> >  2 files changed, 6 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 46d9de54179e..97657fb63af6 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -93,6 +93,9 @@
> >  #define RISCV_ISA_EXT_ZCMOP		84
> >  #define RISCV_ISA_EXT_ZAWRS		85
> >  #define RISCV_ISA_EXT_SVVPTC		86
> > +#define RISCV_ISA_EXT_ZFBFMIN		87
> > +#define RISCV_ISA_EXT_ZVFBFMIN		88
> > +#define RISCV_ISA_EXT_ZVFBFWMA		89
> >  
> >  #define RISCV_ISA_EXT_XLINUXENVCFG	127
> >  
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3a8eeaa9310c..1b286f5bc591 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -325,6 +325,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >  	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> >  	__RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
> >  	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
> > +	__RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN),
> >  	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
> >  	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
> >  	__RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
> > @@ -357,6 +358,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >  	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> >  	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> >  	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> > +	__RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN),
> > +	__RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA),
> 
> @Conor,
> 
> Should we wait for your V/F validation support to be merged before this
> one ?

Uh, I don't really see a reason to hold this up on my account. I can
easily rebase on top when I get the motivation to do more work on that
series.

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