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Message-ID: <CA+V-a8t6b6cbn+q7y9eUgoEx=y0uVrZytp88+dRmepipnwyyUA@mail.gmail.com>
Date: Mon, 4 Nov 2024 12:24:14 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/2] clk: renesas: r9a09g057-cpg: Add support for PLLVDO,
 CRU clocks, and resets

Hi Geert,

Thank you for the review.

On Wed, Oct 30, 2024 at 4:57 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> s/r9a09g057-cpg/r9a09g057/
>
I will fix this as part of v2.

Cheers,
Prabhakar

> On Mon, Oct 28, 2024 at 10:29 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add support for the PLLVDO clock and its related CRU clocks and reset
> > entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated
> > clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and
> > `CLK_PLLVDO_CRU3`, along with their corresponding dividers.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

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